Parallel Clock Level Shifter for Balanced Edge Delay
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Solution Overview
Problem
Existing level shifters in system-on-chip (SoC) designs face challenges in maintaining identical delay times between rising and falling edges of clocks across different voltage domains, which affects the reliability and duty ratios of output clocks.
Innovation Solution
A level shifter design featuring first and second voltage shifter circuits with the same structure, connected in parallel, which include CMOS inverters operating at different voltage domains to synchronize and generate a second clock with identical delay times for both rising and falling edges, ensuring consistent duty ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single voltage shifter circuit is used to convert clock signals between voltage domains, then the circuit complexity is low, but the delay times between rising and falling edges cannot be kept identical, affecting duty ratio accuracy
Solution Approach 1:
The voltage shifter circuit is divided into two parallel paths: a first voltage shifter circuit converting from first voltage domain to second voltage domain, and a second voltage shifter circuit converting from second voltage domain to first voltage domain. Each path includes inverters and transmission gates configured to independently control rising and falling edge delays, enabling precise duty ratio adjustment while maintaining circuit manageability
Solution Approach 2:
The circuit uses controllable transmission gates with adjustable conductance parameters to modify the delay times of rising and falling edges independently. By changing the conductivity parameters of these transmission gates, the circuit can compensate for process variations and temperature effects, maintaining identical delay times and accurate duty ratios across different operating conditions
2Speed
If different voltage levels are used for processor and IP blocks to improve processor performance, then the processor operating speed increases, but additional level shifting components are required, increasing overall system complexity
Solution Approach 1:
The voltage shifter circuit serves multiple functions: it converts clock signals between voltage domains, adjusts duty ratios to be exactly 50%, and compensates for process and temperature variations. This multi-functional design eliminates the need for separate duty ratio correction circuits, reducing overall system complexity while enabling the processor to operate at higher speeds with a different voltage domain
Solution Approach 2:
The circuit incorporates feedback mechanisms where the output of one voltage shifter path influences the control signals of the other path. The transmission gates are controlled by signals that reflect the actual delay characteristics, enabling automatic adjustment to maintain identical rising and falling edge delays despite variations in operating conditions
Data Source
AI summary
Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.