Parallel Clock Tree Timing Pessimism Reduction
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Solution Overview
Problem
Existing static timing tools, such as EinsTimer, face challenges in reducing timing pessimism for parallel clock trees due to the requirement that all non-common gates must be within a bounding box, which is not feasible for complete topologies, leading to inefficiencies in variation penalty reduction.
Innovation Solution
A parallel path proximity credit algorithm is introduced to enhance common path tracing algorithms by assigning a proximity credit to pairs of gates in close proximity, tracing back from clock and data test points to the starting point, and then forward to diverge points, applying credits when gates are near each other, thereby reducing timing pessimism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a bounding box constraint is applied to include all non-common gates for timing analysis, then timing pessimism reduction is achieved, but the method becomes inapplicable to complete parallel clock tree topologies
Solution Approach 1:
The patent segments the parallel clock tree analysis into multiple bounding box regions, each containing a subset of non-common gates. Instead of requiring all gates to fit in one bounding box, the methodology divides them into separate regions (e.g., first bounding box for first set of gates, second bounding box for second set of gates), allowing complete topologies to be analyzed while still achieving timing pessimism reduction for each segment.
2Manufacturing precision
If parallel clock trees are built with gates placed near each other to reduce variation penalty, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by focusing timing analysis on specific local regions (bounding boxes) where gates are placed near each other, rather than requiring global optimization of the entire clock tree. This allows gates within each local bounding box region to benefit from reduced variation due to proximity, while the overall device complexity is managed by analyzing each local region independently.
Data Source
AI summary
A computer-implemented method, system, and computer program product are provided for implementing timing pessimism reduction for parallel clock trees. A common path tracing algorithm in a static timing tool is enhanced to include a proximity credit used for pairs of gates in two clock trees that are placed in close proximity to each other. The proximity credit given is equal to a predefined fraction of a proximity component of a gate delay.