Auto-generating Parallel Code for Multi-Core Processors

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Solution Overview

Problem

Current techniques for producing parallelized or concurrent application code for multi-core processors are prone to human error and place a significant burden on programmers, and are limited by serial operations and communication overhead, which hinder the full benefits of parallel processing.

Innovation Solution

A code generation system comprising a model analyzer, model partitioner, and code generator that identifies data dependencies, computes data and computation maps, and generates parallelized code and inter-core communication code to efficiently map tasks across multiple cores, reducing human error and optimizing parallel processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If parallel processing is implemented on multi-core processors, then processing time is reduced, but communication overhead between cores increases

Engineering Contradiction:
Improveprocessing timeVSAvoidcommunication overhead
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments the application code automatically into parallel tasks that can be executed on different cores, eliminating the need for manual parallelization while optimizing the distribution of computational work across multiple cores to minimize communication overhead

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs self-service by automatically analyzing sequential code and generating parallelized versions without requiring programmer intervention, thus reducing human burden while maintaining processing efficiency

Inventive Principle:
Principle #25Self-service

2Productivity

If manual parallelization is performed by programmers, then code can be optimized for multi-core processors, but human error increases and programmer burden increases

Engineering Contradiction:
Improveparallel processing optimizationVSAvoidhuman error
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system enables self-service by automatically analyzing sequential application code and generating optimized parallel versions without programmer intervention, eliminating human error associated with manual parallelization while maintaining code optimization

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent replaces the mechanical process of manual code analysis and parallelization with an automated computational system that uses algorithms to analyze data dependencies and generate parallelized code, thereby eliminating human burden and error

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If more cores are used for parallel processing, then processing capacity increases, but inter-core communication overhead increases

Engineering Contradiction:
Improveprocessing capacityVSAvoidcommunication overhead
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The system segments computational tasks and intelligently distributes them across available cores based on data dependencies and communication requirements, maximizing processing capacity while minimizing the number of inter-core communications needed

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8661424B2Auto-generation of concurrent code for multi-core applications
Publication Date: 2014.02.25 HONEYWELL INTERNATIONAL INC
  • US8661424B2 patent drawing
  • US8661424B2 patent drawing
  • US8661424B2 patent drawing

AI summary

A code generation system comprises a model analyzer configured to identify data dependencies in a data flow diagram that describes functional behavior of an application, wherein the model analyzer is further configured to compute a data and computation map based on the data dependencies and to compute one or more implementation constraints; a model partitioner configured to compute one or more partition boundaries based on the data and computation map and the one or more implementation constraints; and a code generator configured to generate parallelized code based on the data flow diagram, the one or more implementation constraints, and the one or more partition boundaries, wherein the code generator is configured to map the code corresponding to each partition defined by the one or more partition boundaries to one of a plurality of cores of a multi-core processor, and to generate inter-core communication code for at least one line of the data and computation map crossed by the one or more partition boundaries.