Parallel Codec Core Synchronization for Higher Video Frame Rates

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional single-core video codecs struggle to meet the increased frame rates required for higher video resolutions such as Ultra High Definition (UHD), as the number of frames to be encoded and decoded per second dramatically increases.

Innovation Solution

A parallel encoding and decoding method and apparatus that involves acquiring a synchronization node corresponding to a codec core, transmitting a frame synchronization detection request, acquiring a frame synchronization result, and determining an encoding and decoding mode based on the result to enable parallel encoding and decoding of frames across multiple codec cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single-core codec is used for encoding and decoding, then the device complexity is low, but the frame rate cannot meet the requirements of higher video resolutions

Engineering Contradiction:
Improveframe rateVSAvoidcodec core configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the video encoding and decoding task into separate units that can be processed by multiple codec cores in parallel. Each codec core processes independent video frames or blocks, allowing the system to handle higher frame rates by distributing the workload across multiple cores rather than relying on a single core.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a synchronization dimension to coordinate parallel processing across multiple codec cores. By adding synchronization mechanisms that track and coordinate the processing states of different frames across cores, the system achieves parallel productivity improvement without complete system complexity explosion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple codec cores are used for parallel encoding and decoding, then the frame rate is improved, but the synchronization complexity increases

Engineering Contradiction:
Improveframe rateVSAvoidsynchronization mechanism
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where codec cores report their processing status to a synchronization manager. This feedback loop allows the system to track which frames are ready, which are being processed, and coordinate resource allocation accordingly, managing the complexity of parallel synchronization through systematic status monitoring and response.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces a synchronization node or manager as an intermediary component that coordinates between multiple codec cores. This intermediary handles the complexity of synchronization by centralizing the tracking and coordination of frame processing states, allowing individual cores to focus on their encoding/decoding tasks while the mediator manages the overall synchronization.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If frame synchronization detection is performed to enable parallel processing, then the encoding and decoding accuracy is improved, but the processing time increases

Engineering Contradiction:
Improveencoding and decoding accuracyVSAvoidsynchronization detection time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent performs synchronization status detection and frame readiness assessment in advance before the actual encoding and decoding processing begins. By determining which frames are ready for parallel processing and establishing the synchronization state beforehand, the system minimizes interruptions and waits during the main processing operation, reducing overall time loss.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuous monitoring of frame processing status across all codec cores, ensuring that synchronization information is always available when needed. This continuous state tracking allows the system to immediately begin processing once frames are ready, eliminating idle waiting time and maintaining continuous productive action across all cores.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12348744B2Parallel encoding and decoding method and apparatus, computer device, and storage medium
Publication Date: 2025.07.01 GLENFLY TECH CO LTD
  • US12348744B2 patent drawing
  • US12348744B2 patent drawing
  • US12348744B2 patent drawing

AI summary

Disclosed are parallel encoding and decoding method and apparatus, a computer device, a storage medium, and a computer program product. The method includes: acquiring a synchronization node corresponding to a codec core, and transmitting a frame synchronization detection request to the synchronization node based on a frame to be encoded and decoded; acquiring a frame synchronization result corresponding to the frame synchronization detection request; and determining a encoding and decoding mode for the frame to be encoded and decoded based on the frame synchronization result, and encoding and decoding the frame to be encoded and decoded based on the encoding and decoding mode. By using the method, a plurality of codec cores can be employed to code and decode different frames in the same video in parallel, thereby improving the frame rate.