Parallel Coefficient Sampling and Shuffling for Faster PQC Signatures
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Solution Overview
Problem
The performance of lattice-based post-quantum cryptography (PQC) algorithms is bottlenecked by the execution speed of the SampleInBall algorithm, which pseudorandomly samples polynomials with coefficients in {−1, 0, 1} and Hamming weight τ, critical for subsequent operations.
Innovation Solution
An efficient memory-based architecture for lattice-based cryptography that parallelizes rejection sampling and shuffling of polynomial coefficients, using a Keccak random number generator and a Fisher-Yates shuffle to reduce hardware resources and latency, optimizing the SampleInBall algorithm for high-performance cryptographic systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the SampleInBall algorithm is implemented with sequential rejection sampling and shuffling, then the implementation is simpler, but the execution speed is too slow to meet performance requirements
Solution Approach 1:
The patent divides the polynomial coefficient generation into multiple independent batches, where each batch generates a subset of coefficients through parallel rejection sampling. This segmentation allows simultaneous processing of multiple coefficients without requiring complex sequential dependencies, thereby increasing execution speed while keeping individual sampling units relatively simple
Solution Approach 2:
The patent transitions from sequential single-threaded sampling to multi-threaded parallel sampling, adding a temporal dimension to the coefficient generation process. Multiple threads simultaneously perform rejection sampling for different coefficient positions, converting a time-sequential operation into a spatially-parallel operation that achieves higher throughput
2Productivity
If parallel rejection sampling is implemented to speed up coefficient generation, then execution speed improves, but hardware resources increase
Solution Approach 1:
The patent combines multiple rejection sampling operations into a unified parallel processing framework where threads share common resources such as random number generation, validity checking logic, and memory access patterns. This merging reduces redundant hardware resources while maintaining high throughput through efficient resource sharing among parallel threads
Solution Approach 2:
The patent designs universal sampling units that can handle multiple coefficient positions with the same hardware logic. The rejection sampling module is configured to process different polynomial positions using identical circuitry, making the hardware multi-functional and reducing the need for dedicated resources for each coefficient position
3Reliability
If the Fisher-Yates shuffle is implemented to randomize coefficient positions, then the cryptographic security is improved, but the latency increases
Solution Approach 1:
The patent performs the Fisher-Yates shuffle operation in parallel with the rejection sampling process rather than sequentially after all coefficients are generated. The shuffling begins as soon as the first valid coefficients are obtained, and continues concurrently with subsequent sampling operations, thereby eliminating idle waiting time and reducing total latency
Solution Approach 2:
The patent ensures that the shuffling operation continues continuously without interruption throughout the coefficient generation process. Rather than pausing sampling to complete shuffling, the system maintains continuous useful action by overlapping both operations, ensuring cryptographic security is maintained while minimizing time loss
4Loss of energy
If more coefficient samples are processed in parallel, then the rejection rate decreases, but the circuit footprint increases
Solution Approach 1:
The patent implements rejection sampling with locally optimized validity checking for each coefficient position based on the specific requirements of that position. Rather than using a uniform high-degree polynomial check for all positions, the system adjusts the checking strictness locally, allowing more aggressive parallel sampling while maintaining overall correctness and reducing rejection rates
Data Source
AI summary
A method provides lattice based cryptographic system pseudorandom polynomial coefficients by repetitively receiving sets of n coefficient samples of a random bit string, where n is at least four, repetitively rejection sampling n coefficient samples in parallel to identify valid coefficients, performing a random shuffle of the valid coefficients, and storing sets of n shuffled coefficients in a memory each address configured to hold n coefficients.