Parallel Color Signal Processing via Asymmetric Memory Buffering
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Solution Overview
Problem
Existing image processing systems face inefficiencies in data transfer and processing speed due to the difference in processing capabilities between first and second processing units, leading to increased waiting times and reduced performance, especially when handling large data sizes requiring real-time processing.
Innovation Solution
An information processing device is designed with a first processing unit that processes multiple color signals in parallel and outputs them to a memory, while a second processing unit reads these signals sequentially from the memory, where the reading speed is faster than the writing speed, allowing for direct transfer without a bus and reducing data transfer via the bus, thereby enhancing overall performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a first processing unit processes multiple color signals in parallel and outputs to memory while a second processing unit reads sequentially, then data transfer speed increases, but waiting time increases when reading speed is slower than writing speed
Solution Approach 1:
The patent introduces a memory as an intermediary buffer between the first processing unit (parallel writer) and the second processing unit (sequential reader). This mediator allows the faster parallel writing to proceed without blocking the slower sequential reading, and vice versa, thereby increasing overall data transfer speed while managing waiting times through the buffer capacity of the memory.
Solution Approach 2:
The first processing unit performs preliminary action by writing multiple color signals to the memory in parallel before the second processing unit reads them sequentially. This preliminary parallel writing prepares the data in advance, allowing the second unit to read at its own pace without causing bottlenecks, thus improving data transfer speed while controlling waiting times.
2Productivity
If reading speed from memory is faster than writing speed to memory, then processing efficiency improves, but data synchronization becomes more difficult
Solution Approach 1:
The patent implements feedback mechanisms through status flags (write completion flag, read completion flag) and control logic that monitors the synchronization state between writing and reading operations. When the reading speed exceeds writing speed, the feedback system detects this condition and adjusts the reading operation accordingly, ensuring data synchronization is maintained while still allowing the faster reading capability to improve processing efficiency.
3Speed
If direct transfer between processing units is implemented without bus, then data transfer speed increases, but device complexity increases
Solution Approach 1:
The memory serves as an intermediary that enables direct transfer between the first and second processing units without requiring a shared bus. The first unit writes directly to memory addresses, and the second unit reads directly from those addresses, creating a direct communication path that increases data transfer speed while the memory management logic handles the complexity of coordination.
Data Source
AI summary
An information processing device includes: a first processing unit that processes plural color signals at a time and outputs a processed plural color signals in parallel; a memory that temporarily stores the processed plural color signals outputted in parallel from the first processing unit; and a second processing unit that reads the processed plural color signals from the memory in order by a processable number at a time, the second processing unit being able to process a smaller number of color signals than the first processing unit at a time, wherein a reading speed from the memory is faster than a writing speed to the memory.