Parallel Command Address Encoding in NAND Flash Memory
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Solution Overview
Problem
The command and addressing sequencing time in NAND flash memory devices remains a bottleneck, limiting overall system performance and scalability, as existing methods are not efficiently scalable and require the use of an I/O bus for operation.
Innovation Solution
A novel command/address sequence that encodes bit information on existing clock signals, allowing the controller to decode command and address codes without the need for an I/O bus, enabling parallel execution with data operations and eliminating the sequencing bottleneck.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If command and address sequencing is performed using existing I/O bus methods, then compatibility with existing systems is maintained, but system performance is limited and scalability is poor
Solution Approach 1:
The patent transitions from sequential command/address transmission over the I/O bus to parallel encoding of command and address bits directly onto clock signals. This dimensional change from serial to parallel transmission enables simultaneous execution of command sequencing and data operations, resolving the performance bottleneck while maintaining compatibility through the use of existing clock signal infrastructure.
Solution Approach 2:
The controller performs command and address sequencing in advance by encoding information onto clock signals before data transfer begins. This preliminary action allows the command/address sequence to be prepared and executed concurrently with data operations, eliminating the sequential dependency that limited previous systems and enabling improved scalability.
2Productivity
If command and address sequencing is performed sequentially before data operations, then system simplicity is maintained, but overall operation time increases
Solution Approach 1:
The patent enables continuous useful action by overlapping command/address sequencing with data operations. The controller encodes command and address information onto clock signals during the same time period as data transfer, eliminating idle waiting time and ensuring that the system operates at full capacity throughout the entire operation cycle.
Solution Approach 2:
Command and address information is prepared and encoded onto clock signals in advance of data transfer. This preliminary encoding allows the sequencing to begin before data operations start, and both processes execute simultaneously, thereby reducing the total time loss associated with sequential execution.
3Ease of operation
If an I/O bus is used for command and address transmission, then system compatibility is maintained, but device complexity increases
Solution Approach 1:
The patent applies universality by utilizing existing clock signals for multiple purposes: both timing synchronization and command/address information transmission. This multi-functionality eliminates the need for separate I/O bus infrastructure, maintaining system compatibility while reducing device complexity through the reuse of existing components.
Solution Approach 2:
The existing clock signal infrastructure serves itself by simultaneously providing timing functions and carrying command/address information. This self-service approach eliminates the need for additional dedicated transmission lines, thereby reducing device complexity while preserving compatibility with existing system architectures.
Data Source
AI summary
A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.