Parallel Command Address Sequencing in NAND Flash Memory
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Solution Overview
Problem
The command and address sequencing time in NAND flash memory devices remains a bottleneck, limiting overall system performance, as existing methods to increase sequencing speed are not scalable and are not effectively integrated with data operations.
Innovation Solution
The proposed solution involves utilizing an existing test interface, previously used only for manufacturing, to perform command and address sequencing in parallel with data operations, eliminating the need for an I/O bus and allowing these sequences to be executed in the background, thereby reducing processing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If command and address sequencing is performed sequentially before data operations, then the NAND device can properly execute read/write operations, but the sequencing time becomes a bottleneck limiting overall system performance
Solution Approach 1:
The patent performs command and address sequencing in advance by loading commands and addresses into buffers before the actual data read/write operation begins. This preliminary action allows the sequencing to be completed beforehand, so it does not delay the main data transfer operation, thereby improving overall system productivity while ensuring reliable execution.
Solution Approach 2:
The patent divides the command and address sequencing process into separate segments that can be handled independently from the data transfer operation. By segmenting the sequencing into distinct phases (command loading, address loading, execution) that occur in parallel with data operations, the system achieves both reliable sequencing and improved productivity.
2Speed
If existing methods are used to increase sequencing speed, then command execution becomes faster, but the methods are not scalable and do not integrate effectively with data operations
Solution Approach 1:
The patent creates a universal interface that handles both command sequencing and data transfer operations through the same bus structure. The command bus and data bus share common infrastructure, allowing the system to scale efficiently and integrate seamlessly without requiring separate specialized pathways, thus maintaining adaptability and versatility.
Solution Approach 2:
The patent introduces a time dimension to the command sequencing by performing it in parallel with data operations rather than sequentially. This dimensional change from sequential to parallel execution allows faster command execution while maintaining full integration with data operations, achieving both speed improvement and scalability.
3Productivity
If command and address sequencing is performed in parallel with data operations, then processing overhead is reduced and system efficiency improves, but a separate interface mechanism is required
Solution Approach 1:
The patent merges the command interface and data interface into a unified bus structure, combining previously separate functions into a single integrated system. This merging reduces the need for additional separate interface mechanisms while enabling parallel operation, thus improving productivity without significantly increasing device complexity.
Solution Approach 2:
The patent enables the command sequencing mechanism to serve dual purposes: it handles both command execution and data transfer functions. This self-service approach allows the same interface infrastructure to support parallel operations, reducing the need for additional dedicated interfaces and minimizing the increase in device complexity.
Data Source
AI summary
A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.