Parallel Comparator ADC With Common Input Stage for Faster Conversion
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Solution Overview
Problem
Successive-approximation register (SAR) based Analog-to-Digital Converters (ADCs) face limitations in speed and complexity due to the use of a single comparator, which results in increased power consumption and noise, and the need for complex logic to control the Digital to Analog Converter (DAC) and sample and hold circuitry.
Innovation Solution
The proposed ADC employs a common trans-conductance input stage and multiple parallel comparators, where each comparator works as a separate latch, eliminating reset delays and reducing logical complexities, allowing for sequential activation of comparators without separate SAR logic, thus achieving faster conversion speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single comparator is used in SAR-based ADC, then the device complexity is reduced, but the conversion speed decreases and power consumption increases
Solution Approach 1:
The patent divides the comparison function into multiple parallel comparators (first comparator, second comparator, third comparator) that operate simultaneously on different voltage ranges. This segmentation allows the ADC to determine multiple bits in parallel during a single conversion cycle, thereby increasing conversion speed while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent transitions from sequential single-comparator operation to parallel multi-comparator operation by adding a spatial dimension to the comparison process. Multiple comparators are arranged in parallel to handle different voltage segments simultaneously, converting a time-sequential process into a spatially-parallel process that achieves faster conversion without proportionally increasing overall system complexity.
2Device complexity
If a single comparator is used in SAR-based ADC, then the device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent segments the conversion process into multiple parallel comparators that each handle specific voltage ranges and bit determinations independently. This allows for more efficient power distribution and management, where each comparator operates at optimized power levels for its specific function, reducing overall power consumption compared to a single high-power comparator operating sequentially.
Solution Approach 2:
The patent enables continuous parallel operation of multiple comparators throughout the conversion cycle, eliminating the idle time and repeated startup overhead inherent in sequential single-comparator operation. All comparators perform useful comparison work simultaneously during each conversion cycle, improving energy efficiency by ensuring continuous productive operation of all comparator resources.
3Speed
If multiple parallel comparators are used, then conversion speed increases, but device complexity increases
Solution Approach 1:
The patent merges the control functions of multiple comparators into a unified SAR logic structure that coordinates all comparators through shared control signals and common feedback paths. This consolidation reduces the overall control complexity compared to managing multiple independent comparator systems, as the SAR logic provides centralized coordination for the parallel comparators.
Solution Approach 2:
The patent designs the comparators with universal functionality where each comparator can handle multiple bits of conversion through shared control mechanisms. The first, second, and third comparators all operate under unified SAR control to determine different bits (first bit, second bit, third bit) within the same conversion cycle, reducing control complexity through multi-functional parallel operation.
4Speed
If multiple parallel comparators are used, then conversion speed increases, but noise increases
Solution Approach 1:
The patent segments the voltage comparison range into distinct segments handled by different comparators (first comparator for first voltage range, second comparator for second voltage range, third comparator for third voltage range). This segmentation isolates the noise generated by each comparator to its specific voltage segment, preventing noise propagation across the full dynamic range and allowing for targeted noise management in each segment.
Solution Approach 2:
The patent applies local quality optimization by designing each comparator to operate optimally within its specific voltage range and noise environment. The first, second, and third comparators are configured with local compensation and reference structures tailored to their respective voltage segments, reducing noise impact locally while maintaining high-speed operation across the entire ADC input range.
Data Source
AI summary
An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.