Parallel Comparator Circuit for Merging Data Streams

The patent divides the data sorting problem into multiple parallel streams, where each stream is processed independently through dedicated comparator circuits. The routing circuit segments the input data into N parallel paths, allowing simultaneous processing of multiple data elements. This segmentation enables the system to handle large volumes of data without requiring a single monolithic sorting network, thus reducing overall device complexity while maintaining high productivity.

The patent transitions from traditional sequential sorting to a parallel processing architecture by introducing multiple comparator circuits operating simultaneously across N parallel streams. This dimensional change from 1D sequential comparison to ND parallel comparison enables the system to process data at higher rates without proportionally increasing circuit complexity, as the parallel structure distributes the sorting workload across multiple independent processing paths.

Instead of using a single large sorting network with many comparators, the patent segments the sorting function into N parallel comparator circuits, each handling a specific stream of data. This segmentation maintains sorting accuracy for each individual stream while reducing the complexity of any single comparator unit. The routing circuit coordinates these segmented comparators to produce overall sorted output, achieving high sorting precision without requiring a monolithic complex comparator structure.

The patent employs N comparators to process N parallel streams simultaneously, which provides sufficient sorting capability for the required data volume without over-provisioning. Each comparator performs partial sorting on its designated stream, and the collective action of all comparators achieves complete sorting of the combined input. This partial action approach avoids the excessive complexity that would result from using a single comparator handling all data sequentially.

The patent introduces parallelism as a new dimension in data processing by implementing N parallel comparator circuits that operate simultaneously on N different data streams. This transitions the system from 1D sequential processing to ND parallel processing, enabling the circuit to handle multiple data elements in each clock cycle. The routing circuit manages this parallel architecture by directing input data to the appropriate parallel comparators, achieving high productivity without requiring an excessively complex interconnection structure.

The routing circuit performs preliminary routing of input data to the appropriate parallel comparator streams before the comparison operation begins. This preliminary action organizes the input data in advance, allowing the parallel comparators to operate efficiently without requiring complex real-time arbitration during the comparison phase. By preparing the data distribution beforehand, the system achieves high parallel processing rates with manageable circuit complexity.