Parallel Memory Compression Lanes With Shared Dictionary Access
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Solution Overview
Problem
In computing systems, the CPU is often occupied with data compression and decompression tasks, leading to reduced availability for processing other operations and causing delays for multiple processors, especially when dealing with large amounts of data from multiple software applications, resulting in performance issues due to limited cache memory storage and latency in data swapping.
Innovation Solution
A computing system with a processor that includes a compression/decompression unit with multiple hardware lanes, allowing parallel processing of data compression and decompression using dictionary-based and statistical algorithms, enabling the CPU to remain available for other operations while handling compression and decompression tasks efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU performs data compression and decompression tasks, then data processing capability is improved, but CPU availability for other operations deteriorates
Solution Approach 1:
The patent extracts the compression and decompression functionality from the CPU by implementing dedicated hardware compression/decompression units. These specialized units handle compression tasks independently, allowing the CPU to focus on other operations while maintaining high data processing capability through hardware-accelerated compression.
Solution Approach 2:
The patent introduces compression/decompression units as intermediary components between the CPU and memory systems. These units act as mediators that handle the computationally intensive compression tasks, freeing the CPU from direct involvement in compression operations while still enabling efficient data processing through the intermediary hardware units.
2Device complexity
If a single CPU handles compression for multiple processors, then system complexity is reduced, but processing delay for other processors increases
Solution Approach 1:
The patent segments the compression functionality by providing separate compression/decompression units for different processors. Instead of a single shared CPU handling all compression tasks, each processor has its own dedicated compression unit, eliminating processing delays while maintaining manageable system complexity through modular architecture.
Solution Approach 2:
The patent transitions from a single-dimensional CPU-based compression model to a multi-dimensional architecture where multiple processors each have dedicated compression units. This dimensional expansion allows parallel compression operations without creating bottlenecks, as each processor operates independently with its own compression hardware.
3Quantity of substance
If data is compressed to reduce storage amount, then storage efficiency is improved, but processing time for compression increases
Solution Approach 1:
The patent replaces the software-based compression mechanism (CPU executing compression algorithms) with hardware-based compression units. This substitution of mechanical/computational approach with dedicated hardware circuitry significantly reduces processing time while maintaining effective data compression, as hardware operations execute in parallel and with lower latency than software routines.
Data Source
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AI summary
Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.