Parallel Computational Cores for Noisy Data Stream Processing
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Solution Overview
Problem
Conventional Turing-machine based computers face limitations in processing unpredictable and noisy real-world signals, such as speech recognition and string matching, due to high computational complexity and memory bottlenecks, which are not efficiently addressed by existing technologies.
Innovation Solution
A system utilizing a plurality of computational cores with a liquid section and a linker section, where each core is randomly programmed to process data streams in parallel, allowing for adaptive and asynchronous processing without the need for memory access, thereby enhancing throughput and handling noisy data effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If Turing-machine based computers are used to process unpredictable real-world signals, then computational power can be increased by adding more transistors, but memory access becomes a bottleneck and synchronization becomes impossible
Solution Approach 1:
The system divides the computational task into multiple independent streams processed by separate computational units. Each unit handles a portion of the data stream independently, eliminating the need for centralized memory access and synchronization. This segmentation allows parallel processing without the bottlenecks of traditional memory-bound architectures.
Solution Approach 2:
The computational units are designed with universal functionality to handle multiple types of operations (classification, filtering, transformation) on different data streams simultaneously. This multi-functionality allows the same hardware structure to process diverse real-world signals without requiring specialized memory access patterns for each operation type.
2Power
If more transistors are added to increase computational power, then processing capability improves, but fabrication cost and design verification difficulty increase
Solution Approach 1:
Instead of designing and verifying a single complex high-power processor, the system uses multiple copies of a simpler, verified computational unit. Each unit processes a portion of the data stream, achieving high overall computational power through parallelism rather than through increasing the complexity of individual units. This approach reduces fabrication cost and design verification difficulty while maintaining high computational capability.
3Loss of time
If traditional memory-based processing is used, then data can be stored and accessed, but processing speed is limited by memory access time
Solution Approach 1:
The system extracts and eliminates the memory access bottleneck from the processing pipeline. Computational units operate on data streams directly without requiring intermediate storage in traditional memory structures. This extraction of the memory dependency allows processing to proceed at the speed of computation rather than being limited by memory access time, while reducing the complexity of memory architecture.
4Ease of operation
If synchronous processing is used for deterministic computation, then coordination is simplified, but handling of unpredictable real-world signals becomes inefficient
Solution Approach 1:
The system transitions from static synchronous processing to dynamic asynchronous processing. Computational units operate independently at different speeds and can dynamically adjust their processing rate based on the characteristics of the input data stream. This dynamic approach maintains coordination simplicity through event-driven communication while significantly improving adaptability to unpredictable real-world signals.
Data Source
AI summary
An apparatus for identification of an input data against one or more learned signals is provided. The apparatus comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core being able to independently produce an output indicating recognition of a previously learned signal, the apparatus being further configured to process the produced outputs from the number of computational cores and determining an identification of the input data based the produced outputs.