Parallel Compute Units for Non-Sequential Instruction Processing
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Solution Overview
Problem
Existing multiple compute unit processors struggle to efficiently process non-sequential instruction streams, particularly in deep pipelined and SIMD processors, due to the need for conditional jumps that disrupt pipeline flow and cannot be parallelized effectively.
Innovation Solution
A method involving a generic instruction stream with an index section and compute section is broadcast to multiple compute units, allowing each unit to select local parameters and adapt the instruction for parallel processing of filter strengths, including nulling values to remove unnecessary terms and maintain pipeline efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conditional jump instructions are used to handle non-sequential processing in single compute unit processors, then filtering accuracy is maintained, but processing speed deteriorates due to pipeline interruptions
Solution Approach 1:
The patent segments the processing logic by dividing the non-sequential instruction stream into multiple parallel compute units (CU0, CU1, CU2, etc.), each handling specific filter strength cases (Bs=0, Bs=1, Bs=2, etc.). This segmentation eliminates the need for sequential jump instructions by distributing different filtering paths to different compute units that execute simultaneously, thereby maintaining filtering accuracy while dramatically improving processing speed.
Solution Approach 2:
The patent introduces dynamic parameter selection where each compute unit dynamically selects its operation based on boundary strength parameters and pixel gradient values. Instead of static sequential jumps, the system dynamically configures which compute unit performs which filtering operation based on local image characteristics, enabling both high accuracy adaptive filtering and high-speed parallel execution.
2Productivity
If multiple compute units are used for parallel processing, then processing speed improves, but the ability to handle non-sequential instructions deteriorates due to jump instruction limitations
Solution Approach 1:
The patent makes each compute unit universal by designing them to handle multiple filter strength cases (Bs=0 through Bs=4) through parameter selection rather than dedicated hardware for each case. Each compute unit can be dynamically configured to perform different filtering operations based on the boundary strength parameters, providing multi-functionality that enables handling of non-sequential adaptive filtering instructions while maintaining parallel processing speed.
Solution Approach 2:
The patent uses parameter changes to enable non-sequential instruction handling in parallel architecture. By varying parameters such as boundary strength (Bs), pixel gradient values (ap, aq), and filter coefficients based on local image characteristics, each compute unit adapts its behavior to handle different filtering scenarios. This parameter-driven approach replaces the need for complex jump instructions while maintaining the ability to handle adaptive non-sequential filtering requirements.
3Productivity
If deep pipelining is implemented in single compute unit processors, then processing throughput improves, but conditional jumps disrupt pipeline flow and reduce efficiency
Solution Approach 1:
The patent ensures continuity of useful action by eliminating jump instructions that disrupt pipeline flow. Instead of sequential execution with conditional jumps, the system uses multiple compute units executing continuously in parallel without interruption. Each compute unit maintains continuous pipeline operation for its assigned filter strength cases, ensuring uninterrupted useful action across the entire processing system and maximizing throughput.
Data Source
AI summary
Accelerating processing of a non-sequential instruction stream on a processor with multiple compute units by broadcasting to a plurality of compute units a generic instruction stream derived from a sequence of instructions; the generic instruction stream including an index section and a compute section; applying the index section to localized data stored in each compute unit to select one of a plurality of stored local parameter sets; and applying in each compute unit the selected set of parameters to the local data according to the compute section to produce each compute unit's localized solution to the generic instruction.