Parallel Computer Synchronization Apparatus with Delay Unit
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Solution Overview
Problem
In parallel computer systems, the fluctuation in synchronization establishment between nodes due to varying arrival times of synchronization messages leads to phase differences in global clocks, particularly when using barrier synchronization based on the butterfly algorithm without CPU intervention.
Innovation Solution
A synchronization apparatus and method that divides parallel processing into stages, with each stage involving communication of synchronization messages between nodes, using a receiving unit, control unit, delay unit, and transmitting unit to manage and delay messages, ensuring synchronization information is stored and transmitted effectively to reduce fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If barrier synchronization based on butterfly algorithm without CPU intervention is used to achieve high-speed synchronization, then synchronization speed is improved, but fluctuation in synchronization establishment occurs due to varying arrival times of synchronization messages
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the minimum transmission time required for synchronization messages to travel between nodes before the actual synchronization process begins. This pre-computed timing information is then used during barrier synchronization to compensate for variations in message arrival times, ensuring that all nodes can establish synchronization reliably without CPU intervention while maintaining high speed.
2Productivity
If hardware-based barrier synchronization apparatus is used to eliminate CPU intermediation for each stage, then synchronization speed is improved, but phase difference in global clocks occurs due to fluctuation in synchronization establishment
Solution Approach 1:
The patent implements feedback by using the pre-calculated minimum transmission time information to adjust and compensate for timing variations during barrier synchronization. The system continuously monitors synchronization message arrival times and uses the stored timing data to correct phase differences, ensuring precise global clock synchronization while maintaining high throughput through hardware-based operation without CPU intermediation.
3Adaptability or versatility
If barrier synchronization divides processing into multiple stages with message transmission between nodes, then parallel processing capability is improved, but fluctuation in synchronization timing occurs due to network variability
Solution Approach 1:
The patent applies preliminary action by pre-measuring and storing the minimum transmission times for synchronization messages between all node pairs before parallel processing begins. This timing information is then used during each stage of barrier synchronization to compensate for network variability, reducing timing fluctuations while maintaining the system's ability to divide processing into multiple parallel stages.
Data Source
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AI summary
A synchronization apparatus includes a receiver that receives data from a synchronization apparatus of another node that performs synchronization with its own node from among the plurality of synchronization apparatuses and extracts synchronization information from the received data, a transmitter that transmits the data to the synchronization apparatus of the other node, a receiving state register that stores the extracted synchronization information, a delay unit that delays the received data by a specified period of time, and a controller that stores the extracted synchronization information and synchronization information from its own controller in the reception state register and causes the transmitter to transmit the data to the other node and returns the data to its own node back to its own controller via the delay unit when the extracted synchronization information and the synchronization information from its own controller are stored in the reception state register.