Parallel Computing Architecture with 3D Stacked Cores and Reducers
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Solution Overview
Problem
Conventional computing systems fail to effectively simulate the human brain's massive parallelism and three-dimensional structure, limiting their ability to perform advanced computing functions like artificial intelligence due to inadequate connectivity and dimensional reduction capabilities.
Innovation Solution
A general-purpose parallel computing architecture with multiple interconnected processing cores, synapse coprocessors, and reducer circuits, designed to enhance communication bandwidth and support advanced computing functions through a multi-level structure that mimics the brain's neural network, utilizing 3D integrated circuit techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional computing systems are used to simulate the human brain, then basic computing functions can be performed, but the connectivity and three-dimensional structure of the brain cannot be substantially matched
Solution Approach 1:
The patent transitions from conventional two-dimensional planar integration to three-dimensional vertical stacking of processing cores and memory structures. This dimensional change enables substantially matching the brain's three-dimensional neural connectivity structure, allowing each core to connect to multiple memory banks and other cores through vertical and lateral interconnects, thereby achieving the required adaptability for brain simulation while managing complexity through structured 3D organization.
Solution Approach 2:
The computing system is segmented into multiple independent processing cores, each capable of autonomous operation and equipped with dedicated memory banks and interconnect structures. This segmentation allows parallel processing across numerous cores, mimicking the brain's distributed neural architecture, and enables the system to achieve high connectivity and adaptability without overwhelming complexity by dividing the system into manageable, replicated units.
2Productivity
If multiple processing cores are used to increase parallel processing capability, then computational throughput is improved, but communication bandwidth between cores becomes a bottleneck
Solution Approach 1:
The patent merges processing cores and memory banks into an integrated three-dimensional architecture where computation and storage are closely coupled. Each processing core is directly connected to multiple memory banks through high-bandwidth vertical interconnects, eliminating the von Neumann bottleneck. This merging of compute and memory resources across multiple dimensions provides abundant communication bandwidth that scales with the number of cores, enabling high productivity in parallel processing without bandwidth constraints.
3Ease of manufacture
If conventional two-dimensional integration is used, then manufacturing is easier, but the ability to rival human brain capabilities is limited
Solution Approach 1:
The patent employs three-dimensional integrated circuit (3D IC) techniques including vertical stacking of processing layers, through-silicon via (TSV) technology for vertical interconnects, and multi-layer routing. These manufacturing techniques enable the construction of complex three-dimensional architectures that substantially match brain structure while remaining compatible with existing semiconductor fabrication processes. The 3D integration approach achieves high computational capability and brain-like adaptability without sacrificing ease of manufacture, as the techniques build upon conventional CMOS fabrication with added vertical dimensionality.
Data Source
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AI summary
An apparatus includes multiple parallel computing cores (102), where each computing core (102) is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple parallel coprocessors (112) associated with each computing core (102). The apparatus further includes multiple communication lines (122, 124) configured to transport the input data from each computing core (102) to a designated one of the coprocessors (112) associated with each of the computing cores (102), where the coprocessors (112) are configured to process the input data and generate output data. In addition, the apparatus includes multiple reducer circuits (115), where each computing core (102) is associated with one of the reducer circuits (115). Each reducer circuit (115) is configured to receive the output data from each of the coprocessors (112) of the associated computing core (102), to apply one or more functions to the output data, and to provide one or more results to the associated computing core (102).