Parallel Computing Synchronization Device for Barrier State Management
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Solution Overview
Problem
Existing parallel computing systems face challenges in achieving high-speed barrier synchronization while preventing the cancellation of waiting states and avoiding the overhead of double barrier synchronization.
Innovation Solution
A synchronization device with a receiver that extracts synchronization information and register selection information, and a controller that alternately stores this information in two receiving state registers, ensuring data transmission only when synchronization is complete, thereby maintaining high-speed synchronization without canceling waiting states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier synchronization is performed successively among multiple computing nodes, then synchronization can be established, but the waiting state of prior barrier synchronization may be canceled by subsequent barrier synchronization messages
Solution Approach 1:
The patent applies preliminary action by setting up a waiting state management mechanism before barrier synchronization occurs. Each computing node maintains a waiting state indicator that is set in advance when a barrier synchronization message is sent. This preliminary setup prevents the waiting state from being accidentally canceled by subsequent messages, as the system checks the waiting state indicator before processing new messages.
Solution Approach 2:
The patent implements feedback by having computing nodes send acknowledgment messages back to confirm barrier synchronization completion. The waiting state management relies on receiving these feedback messages to clear the waiting state indicator. This feedback mechanism ensures that the waiting state is only canceled when proper synchronization confirmation is received, preventing premature or erroneous state transitions.
2Reliability
If a long time interval is set between prior and subsequent barrier synchronization requests, then waiting states are preserved, but synchronization speed is reduced
Solution Approach 1:
The patent uses preliminary action by pre-configuring the waiting state management structure and setting up the mechanism to handle rapid successive barrier synchronization requests. This allows the system to maintain reliability without requiring long time intervals, as the waiting state indicators are ready to be set and checked immediately when messages arrive.
Solution Approach 2:
The patent applies dynamics by making the waiting state management adaptive to the actual timing and sequence of barrier synchronization messages. The system dynamically sets and clears waiting state indicators based on the real-time arrival of messages and acknowledgments, rather than using fixed time intervals. This allows rapid successive synchronization while preserving waiting states when needed.
3Speed
If barrier synchronization is implemented with hardware-based transmission destination modification, then high-speed synchronization is achieved, but the system requires complex hardware components
Solution Approach 1:
The patent uses an intermediary approach by introducing a message queue or buffer mechanism that mediates between the transmission destination modification and the barrier synchronization logic. This intermediary structure allows the hardware to operate at high speed while the complexity of managing multiple transmission destinations is handled through standardized message routing, reducing the overall system complexity.
Solution Approach 2:
The patent applies universality by designing a barrier synchronization device that can handle multiple transmission destinations through a unified message processing mechanism. The same hardware components and logic are used regardless of which destination is being targeted, allowing the system to achieve high speed while managing complexity through reusable, multi-functional elements rather than dedicated hardware for each destination.
Data Source
AI summary
A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first and the second receiving state register.