Parallel Concurrent Test System for Semiconductor Devices
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Solution Overview
Problem
Automated semiconductor test equipment experiences significant idle time due to mechanical manipulations, limiting the efficiency and cost-effectiveness of testing processes, particularly in semiconductor manufacturing where reducing index time can lead to substantial economic gains.
Innovation Solution
Implementing a Parallel Concurrent Test (PCT) system that reconfigures sequential test flows into a two-pass test flow using a single integrated handler, allowing for parallel concurrent testing with a pick and place handler and a device under test interface board, which includes broadside and design-for-test sockets, enabling simultaneous broadside and DFT testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mechanical operations speed is increased to reduce index time, then productivity is improved, but device complexity and maintenance costs increase
Solution Approach 1:
The patent replaces mechanical manipulation with magnetic field-based manipulation. Magnetic chucks and magnetic fields are used to pick up, move, and position semiconductor devices without mechanical contact, eliminating the need for complex mechanical manipulators while reducing index time and maintenance requirements.
2Productivity
If sequential testing is used with single socket DIB, then device complexity is reduced, but productivity is worsened due to idle tester time
Solution Approach 1:
The interface board is segmented into multiple test sockets (broadside test socket and DFT test sockets) that can operate independently and concurrently. This allows the tester to perform multiple tests simultaneously on different devices, eliminating idle time and improving productivity without requiring complex reconfiguration.
Solution Approach 2:
The interface board is designed with multi-functionality to support both broadside testing and DFT testing concurrently through different sockets. This universal design allows the same board to handle multiple test types simultaneously, maximizing tester utilization without increasing overall system complexity.
3Productivity
If mechanical manipulation speed is increased, then index time is reduced, but reliability is worsened due to risk of device damage
Solution Approach 1:
The patent replaces mechanical contact-based manipulation with magnetic field-based manipulation. Magnetic chucks provide contactless holding and movement of devices, eliminating mechanical stress, friction, and the risk of dropping or damaging devices while enabling faster index times.
Data Source
AI summary
A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.