Parallel Concurrent Test System for Semiconductor Devices

The patent segments the testing process into two distinct passes: a broadside testing pass and a DFT testing pass. This segmentation allows each pass to be optimized independently, with the broadside pass handling high-speed initial testing and the DFT pass handling detailed functional testing. By dividing the monolithic testing process into separate stages, the system achieves high productivity without requiring all components to operate at maximum speed simultaneously, thereby reducing overall equipment complexity.

The patent introduces a temporal dimension to the testing process by implementing parallel concurrent testing within the broadside pass. Multiple devices are tested simultaneously in different test sockets, transforming a sequential single-device testing approach into a parallel multi-device approach. This dimensional change allows the system to increase productivity by testing multiple devices concurrently rather than requiring faster single-device testing, thus avoiding the need for increasingly complex high-speed mechanical manipulation equipment.

By segmenting the test flow into separate broadside and DFT passes with distinct socket configurations, the patent allows each pass to use manipulation speeds appropriate to its requirements. The broadside pass can use faster speeds for initial placement, while the DFT pass uses slower, more careful manipulation. This segmentation enables productivity improvement in the broadside pass without compromising device integrity in the DFT pass, as each stage can be optimized independently for its specific speed and handling requirements.

The broadside testing pass serves as a preliminary action that screens devices before they undergo the more delicate DFT testing. By performing initial high-speed broadside testing first, the system can identify and remove obviously defective devices before they proceed to the slower, more careful DFT testing stage. This preliminary filtering protects subsequent testing stages from processing known-defective devices, thereby maintaining device integrity while allowing faster overall throughput.

The patent segments the testing process into two distinct passes that can be executed in parallel concurrent fashion. The broadside testing pass and DFT testing pass are separated into different socket configurations, allowing the tester to perform broadside testing on one device while simultaneously performing DFT testing on another device in a different socket. This segmentation transforms the sequential test flow into a parallel structure, dramatically improving tester utilization without requiring complex coordination between multiple testers.

The patent adds a spatial dimension to the testing process by implementing parallel concurrent testing across multiple test sockets. Instead of testing devices sequentially in a single socket, the system uses multiple sockets to test multiple devices simultaneously at different stages of the test flow. This dimensional change from single-socket sequential testing to multi-socket parallel testing increases productivity by keeping the tester continuously utilized across multiple devices, while the underlying system architecture remains relatively simple.