Parallel Configuration of Programmable Logic and Disaggregated Dies
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Solution Overview
Problem
Existing disaggregated system architectures face challenges in efficiently configuring programmable logic devices and disaggregated dies due to increased delays and reduced efficiency caused by routing configuration data through the programmable logic device.
Innovation Solution
The implementation of a system that enables parallel programming of programmable logic devices and disaggregated dies using a first protocol (such as PCIe) and a second protocol (such as CXL) for Compute Express Link interconnect communications, allowing for simultaneous configuration of components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If configuration data is routed through the programmable logic device, then the disaggregated dies can be programmed, but the boot time and configuration efficiency are reduced
Solution Approach 1:
The patent segments the configuration data path by introducing a separate configuration interface for disaggregated dies that bypasses the programmable logic device. This allows configuration data to be delivered directly to dies through dedicated configuration memory and interface circuitry, eliminating the sequential dependency where dies must wait for PLD configuration to complete first.
Solution Approach 2:
The patent introduces configuration memory and dedicated configuration interface circuitry as intermediaries between the host device and disaggregated dies. These intermediaries enable direct configuration data transmission to dies without requiring the programmable logic device to act as a gateway, thus parallelizing the configuration process.
2Reliability
If configuration data is routed through the programmable logic device, then the disaggregated dies can be programmed, but the configuration efficiency is reduced
Solution Approach 1:
The configuration system is segmented into independent paths: one for the programmable logic device and another for disaggregated dies. The second configuration interface and associated configuration memory create a dedicated data path that enables simultaneous configuration operations, eliminating the bottleneck where all configuration must flow through the PLD.
Solution Approach 2:
The patent enables preliminary configuration of disaggregated dies by providing direct configuration access before the PLD is fully operational. The configuration memory can be populated and dies can be programmed in advance or simultaneously with PLD configuration, rather than waiting for sequential completion.
3Device complexity
If sequential configuration is used, then the system is simpler to implement, but the boot time increases
Solution Approach 1:
The patent adds a segmented configuration path with separate interface circuitry and configuration memory for dies, which appears to increase complexity but actually simplifies the overall system by eliminating the need for complex sequential control logic in the PLD. The parallel paths are independently manageable.
Solution Approach 2:
The patent transitions from a one-dimensional sequential configuration approach to a two-dimensional parallel configuration architecture. By adding the dimension of simultaneous configuration operations through separate interfaces, the system achieves faster boot times without requiring exponential increases in complexity.
4Device complexity
If sequential configuration is used, then the configuration architecture is simpler, but the computational cycles increase
Solution Approach 1:
The configuration architecture is segmented into parallel operational paths, allowing computational resources to be utilized simultaneously for both PLD and die configuration. This eliminates idle computational cycles that occur during sequential waiting periods while maintaining manageable architectural complexity through modular interface design.
Data Source
AI summary
Integrated circuit devices, methods, and circuitry that program disaggregated dies and programmable logic devices at least partially in parallel are described herein. A host device may program a programmable logic device using a configuration bitstream having a first protocol and sent via a first portion (e.g., first layer) of a communication link. The host device may program disaggregated dies using image files having a second protocol and sent via a second portion (e.g., second layer) of a communication link. The host device may send the configuration data and the image files at a same or overlapping time since the data may be sent in separate layers of the communication link, thereby avoiding interference.