Parallel Contact Array Layout for High-Power GaN Transistors
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Solution Overview
Problem
Conventional high power transistors with a single linear array of contacts inefficiently utilize circuit package space and heat dissipation, limiting power rating and gain.
Innovation Solution
Designing high power transistors with multiple linear arrays of contacts arranged in parallel to increase total gate width without elongating the die, enhancing power rating and heat dissipation through increased surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single linear array of contacts is used in conventional high power transistors, then the device structure is simple, but the circuit package space utilization is inefficient and heat dissipation is limited
Solution Approach 1:
The patent transitions from a single linear array (one-dimensional arrangement) to multiple linear arrays arranged in parallel (two-dimensional arrangement). This dimensional change allows the contacts to occupy space more efficiently in the circuit package, increasing the total gate width without requiring a proportional increase in the die length, thereby improving space utilization.
Solution Approach 2:
The patent divides the single linear array of contacts into multiple separate linear arrays arranged in parallel. This segmentation allows each array to be independently optimized and positioned to maximize space utilization in the circuit package, while collectively providing a larger total gate width for high power applications.
2Ease of manufacture
If a single linear array of contacts is used in conventional high power transistors, then the device structure is simple, but heat dissipation capability is limited
Solution Approach 1:
By arranging multiple linear arrays of contacts in parallel rather than using a single array, the patent increases the total surface area available for heat dissipation. This dimensional transition from one to multiple arrays provides additional pathways for heat to be conducted away from the active regions, improving thermal management in high power applications.
Solution Approach 2:
The segmentation of the contact structure into multiple parallel arrays creates separate heat dissipation zones. Each array can independently conduct heat away from the semiconductor device, distributing the thermal load across multiple pathways and enhancing overall heat dissipation capability.
3Length of moving object
If the die length is increased to accommodate more contacts, then the total gate width increases, but the circuit package space utilization decreases
Solution Approach 1:
The patent resolves this contradiction by transitioning from increasing gate width through extending the die length (one-dimensional approach) to increasing gate width through adding parallel arrays (two-dimensional approach). This allows the total gate width to increase while maintaining a compact die footprint, thereby improving circuit package space utilization.
Solution Approach 2:
By segmenting the contact structure into multiple parallel arrays, the patent achieves a larger total gate width without requiring a proportional increase in die length. Each array contributes to the total gate width while the parallel arrangement maintains a compact overall structure, optimizing space utilization in the circuit package.
Data Source
AI summary
High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of contacts in parallel. Thereby, the total gate width and the power rating of a high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.