Parallel Control Computing with State Vector Exchange for Fault Detection
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Solution Overview
Problem
Current control systems, particularly in safety-critical applications like railway safety and nuclear power plants, face challenges in achieving an error rate less than 10^-8 errors per operating hour without complex error detection tests, especially when using error-prone FPGAs, and require robust fault-tolerant mechanisms to prevent catastrophic failures.
Innovation Solution
A computerized system with multiple computing units that operate in clocked computing cycles, exchanging and comparing state vectors and output vectors in each cycle to detect errors, triggering safety reactions such as 'all signals on red' or controlled shutdowns, and using unique signatures for data packets to ensure data integrity, thereby eliminating the need for extensive error testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple computing units operate in parallel with extensive error detection tests, then reliability is improved, but device complexity and processing time increase
Solution Approach 1:
The system performs preliminary actions by exchanging state vectors between computing units before final output generation. Each computing unit exchanges its state vector with others in advance, allowing error detection to occur naturally during the computation process rather than requiring separate extensive testing phases. This preliminary exchange mechanism enables the system to detect errors early while maintaining streamlined operations.
Solution Approach 2:
The computing units perform self-service error detection by comparing their own state vectors against received state vectors from other units. Each unit actively participates in verifying the correctness of computations across the system, eliminating the need for centralized or external error detection mechanisms. This self-verification approach reduces overall system complexity while maintaining high reliability through distributed error checking.
2Reliability
If state vectors are exchanged between computing units after each cycle, then error detection capability is improved, but communication overhead and processing time increase
Solution Approach 1:
The system merges the state vector exchange operation with the regular computation cycle, so that error detection occurs simultaneously with normal processing rather than as a separate step. The state vectors are exchanged as part of the standard operational flow between computing units, integrating verification functions into the core computation process. This merging eliminates additional time overhead by making error detection an inherent part of the computational workflow.
3Reliability
If unique signatures are used for data packets, then data integrity is improved, but device complexity increases
Solution Approach 1:
The system uses parameter changes by incorporating unique identifiers (signatures) into the state vectors that are already being exchanged between computing units. Rather than adding separate verification protocols, the signature information is integrated into the existing state vector structure. This approach maintains data integrity through unique identification while avoiding the complexity of separate verification mechanisms, as the signature verification occurs naturally during the existing state vector comparison process.
Data Source
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AI summary
According to one aspect of the invention, a computerized system, in particular a control system, is provided which is configured to determine a new state vector (Zn+1), whose state variables are updated, and an output vector (On), which represents a discrete number of output variables, from an input vector (In) representing a discrete number of input variables and a state vector (Zn) representing a discrete number of state variables. The output variables are intended for controlling at least one device and/or for outputting information. The system has a plurality of processing units which determine the new state vector and the output vector in parallel from the input vector and the state vector. According to the invention, the system is configured such that at least all new state vectors are exchanged between the processing units after each cycle.