Parallel Conversion Circuit With Phase-Based Delay Output
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Solution Overview
Problem
Conventional parallel conversion circuits in high-speed serial transfer systems fail to accurately measure delay time due to phase differences between serial data reception and parallel data output, which is critical for real-time applications like IEEE1588-compliant and PON systems.
Innovation Solution
A parallel conversion circuit that samples serial data using a first clock signal, converts it to parallel signals based on a synchronization pattern timing signal, and retimes the signals using a second clock signal to output delay time information corresponding to the phase difference, utilizing a phase comparison unit with a counter and flip-flop to detect and output this information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If serial data is converted to parallel data using a conventional parallel conversion circuit, then the conversion speed is improved, but the delay time measurement accuracy deteriorates due to phase differences between serial data reception and parallel data output
Solution Approach 1:
A phase comparison unit is introduced as an intermediary component between the parallel conversion circuit and the external system. This unit includes a counter that counts clock cycles from the synchronization pattern timing signal to the second clock signal, and a flip-flop that outputs the counted value as delay time information. This intermediary mechanism enables accurate measurement of the phase difference without affecting the high-speed conversion function.
Solution Approach 2:
The phase comparison unit provides feedback information about the phase difference between the synchronization pattern timing signal and the second clock signal. By counting the number of clock cycles and outputting this count as delay time information, the system creates a feedback mechanism that allows external devices to compensate for or utilize the measured delay, thereby improving overall system timing accuracy.
2Device complexity
If the parallel conversion circuit outputs parallel data without delay information, then the device complexity is reduced, but the adaptability to real-time applications deteriorates
Solution Approach 1:
The parallel conversion circuit is enhanced with multi-functionality by adding the phase comparison unit that performs both the original parallel conversion function and the additional function of measuring and outputting delay time information. The counter and flip-flop in the phase comparison unit enable the circuit to serve multiple purposes: high-speed data conversion and precise delay measurement, making it adaptable to various real-time applications such as PON systems and IEEE1588-compliant systems.
Data Source
AI summary
Disclosed is a serial-to-parallel conversion circuit that detects phase difference between a timing of receiving serial receive data and reconstituting parallel data for each symbol and a timing of outputting the reconstituted parallel data to an inside of an LSI, and outputs the detected phase difference as delay time information.