Parallel Hardware Calculator for Convolution Data Reuse
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Solution Overview
Problem
The existing hardware calculators for convolution product calculations face inefficiencies due to the quadratic increase in inference time with increasing dimensions, where the number of multiplications-accumulations required becomes a time-limiting factor, especially as the number of input data loadings increases.
Innovation Solution
The proposed integrated circuit employs a hardware calculator with two parallel calculation paths that access three registers, allowing for four multiplications-accumulations to be performed with only two loadings of input data, by strategically loading and reusing factors across operations, thereby reducing the number of data loading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of MAC type calculators is multiplied to calculate more output components in parallel, then the calculation throughput is improved, but the number of input data loading processes increases quadratically
Solution Approach 1:
The patent merges the loading operations for multiple calculation paths by having them share common input registers. Instead of each MAC calculator having dedicated loading paths, multiple calculation paths share the same input data loading infrastructure, reducing the total number of loading operations required.
Solution Approach 2:
The input registers are designed to serve multiple calculation paths simultaneously. The same input data can be reused across different MAC calculations by having universal input registers that multiple calculation paths can access, rather than requiring dedicated registers for each path.
2Measurement precision
If the dimension N of convolution product is increased to improve calculation accuracy, then the output quality is improved, but the inference time increases quadratically
Solution Approach 1:
The patent segments the calculation into multiple parallel paths that can simultaneously process different portions of the convolution. By dividing the work across multiple calculation paths that operate in parallel, the total inference time is reduced while maintaining the ability to handle large dimension N for accurate calculations.
Solution Approach 2:
The patent introduces a parallelism dimension to the calculation architecture. Instead of sequentially processing increasing dimensions of N, the system uses multiple calculation paths operating in parallel, effectively adding a temporal/spatial dimension to the computation that reduces the quadratic time complexity.
3Productivity
If the number of input data loadings is increased to support more parallel calculations, then the calculation capacity is improved, but the data loading becomes the time limiting factor
Solution Approach 1:
The patent combines multiple data loading operations into shared input registers that serve multiple calculation paths. By merging the loading infrastructure, the system avoids the bottleneck of multiple sequential loading operations while maintaining high calculation capacity through parallel processing.
Solution Approach 2:
The patent performs preliminary loading of input data into shared registers before the actual MAC calculations begin. This preliminary action ensures that all necessary data is available in the input registers before parallel calculation paths start processing, eliminating waiting time during the calculation phase.
Data Source
AI summary
In an embodiment an integrated circuit includes a hardware calculator configured to calculate in parallel a first output component Yn−1 of a first rank n−1 and a second output component Yn of a second rank n which is higher than and consecutive to the first rank, according to the formula: Ym=Σk=0N−1bkxm−k, in a series of operations, wherein the hardware calculator includes a first calculation path dedicated to the first output component Yn−1, a second calculation path dedicated to the second output component Yn, wherein, for each operation, a first register is configured to contain a pair of first factors {xi, xi−1} corresponding to terms {bkxm−k}[k;k+1]m=n−1 of an operation in the first path, a second register is configured to contain a pair of second factors {bj, bj+1} corresponding to terms {bkxm−k}[k;k+1]m=n−1 of the operation in the first path, and a third register is configured to contain a pair of second factors {bj+2, bj+3} corresponding to terms {bkxm−k}[k+2;k+3]m=n−1 of the next operation in the first path.