Parallel Convolution Processor Architecture for Neural Network Efficiency
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Solution Overview
Problem
Current machine learning techniques, particularly in neural networks for tasks like text, image, and voice recognition, face inefficiencies in parallel data processing, especially in convolutional neural networks, which can lead to increased computational resources and memory requirements.
Innovation Solution
A processor architecture is introduced that includes an input buffer, a data extractor, a multiplier, and an adder, allowing for parallel extraction and multiplication of kernel data with convolution coefficients, and simultaneous calculation of convolution results, optimized to reduce memory requirements and processing cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If convolutional filtering is performed using traditional sequential processing, then computational accuracy is maintained, but processing time and computational resources increase
Solution Approach 1:
The input buffer is divided into multiple segments (first buffer, second buffer, third buffer) that can be processed simultaneously. Each buffer segment handles a portion of the kernel data extraction and multiplication operations, allowing parallel processing of convolution operations across multiple data segments to reduce overall processing time
Solution Approach 2:
The patent transitions from sequential single-threaded processing to parallel multi-threaded processing by organizing the computation across multiple buffer segments and processing threads. This dimensional change in processing architecture enables simultaneous execution of multiple convolution operations that would otherwise be performed sequentially
2Productivity
If more memory is allocated for data storage and intermediate results, then processing capacity increases, but memory requirements and device complexity increase
Solution Approach 1:
The patent combines multiple buffer operations and computation steps into an integrated processing pipeline. The first, second, and third buffers work together in a coordinated manner to perform extraction, multiplication, and accumulation operations simultaneously, reducing the need for separate intermediate storage areas and minimizing overall memory requirements
Solution Approach 2:
Data is pre-organized into buffer segments before processing begins. The input buffer is structured with specific segments prepared in advance for parallel access, allowing the processing units to immediately begin parallel operations without requiring additional intermediate storage for data reorganization during computation
Data Source
AI summary
A method and apparatus for processing data are provided. The processor includes an input buffer, a data extractor, a multiplier, and an adder. The input buffer receives data and stores the data. The data extractor extracts kernel data corresponding to a kernel in the data from the input buffer. The multiplier multiplies the extracted kernel data by a convolution coefficient. The adder calculates a sum of multiplication results from the multiplier.