Parallel CORDIC with Hardwired Bit-Shifts for APSK Signal Processing
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Solution Overview
Problem
Existing CORDIC architectures for digital radio receivers face challenges in balancing low latency, high accuracy, and reduced die area while maintaining high throughput and power efficiency, particularly in interpreting distorted amplitude and phase-shift keying (APSK) signals.
Innovation Solution
A parallel CORDIC implementation with hard-wired bit-shifters and truncated fixed parameter values is used, featuring multiple stages of three-dimensional CORDIC cells with reduced adder/subtractor stages and optimized bit-widths to achieve low bit-error rates and efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a parallel CORDIC implementation is used to achieve high throughput, then processing speed improves, but die area and power consumption increase
Solution Approach 1:
The CORDIC algorithm is divided into multiple parallel stages, each handling a portion of the computational workload. This segmentation allows the system to achieve high throughput through parallel processing while keeping each individual stage compact, thereby managing die area effectively.
Solution Approach 2:
Different stages of the parallel CORDIC implementation use optimized bit-widths and truncated fixed parameter values tailored to their specific computational requirements. This local optimization reduces the overall die area while maintaining the necessary accuracy and throughput for each stage.
2Measurement precision
If full precision is maintained in CORDIC calculations to ensure high accuracy, then bit-error rate decreases, but die area and power consumption increase
Solution Approach 1:
The implementation uses truncated fixed parameter values and optimized bit-widths that are sufficient for achieving low bit-error rates in APSK signal processing. By carefully selecting parameter precision levels, the system maintains high accuracy without the overhead of full precision calculations, thereby reducing die area.
3Loss of time
If multiple parallel CORDIC stages are implemented to reduce latency, then processing speed improves, but power consumption increases
Solution Approach 1:
The computational task is segmented into multiple parallel stages that can operate simultaneously, reducing the overall latency. By distributing the workload across stages with optimized resource allocation, the system achieves low latency while managing power consumption through efficient use of computational resources in each stage.
Data Source
AI summary
A reduced COordinate Rotation DIgital Computer (CORDIC) cell in a parallel CORDIC has an xy-path from x and y inputs to x and y outputs, and a z-path from a z-input to a z-output. Bit-shifts in the xy-path are hardwired. The z-path has a shortened adder/subtractor with a built-in or hardwired fixed parameter. Input bits from the z-input are split into most significant and least significant bits. The number of most significant bits equals the shortened adder/subtractor width. The most significant bits are input to the non-inverting inputs of the adder/subtractor for calculating the most significant z-output bits. The least significant bits are connected directly (or via buffers) from the z-input to the z-output.