Parallel Correlator Implementation Using Block Integration
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Solution Overview
Problem
Current GPS receivers face challenges in achieving efficient acquisition of GPS signals due to the need for a large number of parallel correlators, which demand significant logic resources and high correlation frequencies, making it difficult to realize in Application Specific Integrated Circuits (ASICs) without optimization.
Innovation Solution
The implementation of an IF signal preprocessing technique and block integration method allows for equivalent parallel correlators, reducing correlation frequency, gate counts, and power consumption by generating pre-integration results and using a plurality of block integrators to perform partial correlations in a time division manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of parallel correlators are used to achieve efficient GPS signal acquisition, then the acquisition speed is improved, but the logic resources and device complexity increase significantly
Solution Approach 1:
The patent divides the C/A code into multiple segments and processes them in parallel using a small number of correlators. Instead of using one correlator to process the entire 1023-chip C/A code sequentially, the code is segmented into chunks that can be processed simultaneously by fewer correlators, thereby maintaining acquisition speed while reducing the number of required correlator units.
Solution Approach 2:
The patent introduces a time dimension by processing different segments of the C/A code at different time intervals. Multiple correlators process different segments in parallel, and the results are combined over time to achieve the equivalent effect of a single correlator processing the entire code, thus reducing hardware complexity while maintaining productivity.
2Productivity
If a large number of parallel correlators are used to achieve efficient GPS signal acquisition, then the acquisition speed is improved, but the power consumption increases
Solution Approach 1:
By segmenting the C/A code and using fewer correlators to process these segments in parallel, the patent reduces the total number of active hardware units, thereby lowering power consumption while maintaining the same acquisition speed through parallel processing of code segments.
Solution Approach 2:
The patent combines the processing of multiple C/A code segments across different correlators and time intervals to achieve the same result as a single correlator would produce, thereby reducing the overall power consumption by merging operations that would otherwise require separate hardware resources.
3Productivity
If the correlation frequency is increased to improve signal acquisition speed, then the productivity is improved, but the gate counts and device complexity increase
Solution Approach 1:
The patent performs preliminary processing of the C/A code by segmenting it into manageable chunks before correlation. This preliminary segmentation allows the correlators to work at lower frequencies on smaller data sets, reducing the gate counts required while maintaining overall acquisition speed through the parallel processing of multiple segments.
Data Source
AI summary
An apparatus for processing spread spectrum signals digitized at a predetermined sampling frequency. The apparatus includes an intermediate frequency signal preprocessing unit, a plurality of parallel block integrators. The intermediate frequency signal preprocessing unit is capable of generating pre-integration results based on an input signal and local reference signals at a predetermined rate. The pre-integration results produced by the intermediate frequency signal preprocessing unit are grouped into sets of pre-integration results. Each set of the pre-integration results contains a predetermined number of pre-integration results. The plurality of parallel block integrators is in communication with the intermediate frequency signal preprocessing unit. Each of the block integrators is capable of receiving, in succession, sets of a predetermined number of pre-integration results, and for each set of predetermined number of pre-integration results, each of the block integrators is capable of performing a plurality of partial correlations based on the set of the predetermined number of pre-integration results and a plurality of shifted segments of a pseudorandom noise code until a next set of pre-integration results are received by the block integrator.