Parallel Counter Architecture for High-Speed Multi-Entry Counting
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Solution Overview
Problem
Current counters in integrated circuits, particularly those using on-chip RAM, face challenges in scalability and speed due to high costs and limited processing rates, as they require multiple clock periods to complete counting operations and are not suitable for large-scale applications with high counting application rates.
Innovation Solution
A counter design that includes multiple counting modules with shared counting spaces and a computing module to accumulate values across modules, along with a poll counting mechanism to expand read-write bandwidth, allowing for simultaneous counting of multiple entries and increased processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If counters are constructed by on-chip RAM to reduce cost, then manufacturing cost decreases, but processing speed deteriorates due to requiring multiple clock periods for counting operations
Solution Approach 1:
The counter is divided into multiple counting modules (first counting module, second counting module, etc.), each capable of independent counting operations. This segmentation allows parallel processing of multiple counting entries simultaneously, thereby improving processing speed while maintaining cost-effectiveness through on-chip RAM implementation.
Solution Approach 2:
Multiple counting modules are merged with a shared computing module that accumulates counting results from all modules. The computing module reads and accumulatively computes values from different counting modules to obtain total count values, enabling high-speed parallel counting while consolidating resources to control cost.
2Device complexity
If multiple counting entries share the same counting application sources in on-chip RAM, then device complexity is reduced, but processing speed deteriorates due to sequential counting requirements
Solution Approach 1:
The system segments counting operations into multiple independent counting modules, where each module can process different counting entries simultaneously. This segmentation resolves the conflict by enabling parallel processing while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing multiple counting modules that operate simultaneously on different counting entries. This transforms the sequential single-module approach into a parallel multi-module system, dramatically improving counting application speed without proportionally increasing complexity.
3Productivity
If register-based counters are used to achieve high refreshing rates, then processing speed improves with one count per clock period, but manufacturing cost increases making them unsuitable for large-scale application
Solution Approach 1:
The patent creates multiple copies of counting functionality through parallel counting modules implemented using on-chip RAM. Each counting module is a simplified copy of the counting logic, and their parallel operation achieves high refreshing rates comparable to register-based counters while using cheaper on-chip RAM technology for large-scale deployment.
Data Source
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AI summary
A counter includes: a computing module (100) and N counting modules (101). Each counting module includes a plurality of counting spaces corresponding to different counting entries, and counting spaces of the same counting entry in different counting modules have the same address, wherein the counting module is arranged to provide a value for computing to the computing module in response to a counting application of a counting application source. The computing module is arranged to read values of the same counting entry in different counting modules and accumulate the read values to obtain a total count value of the counting entry, N being an integer not less than 1. Also disclosed is a counting method.