Parallel CRC Block Calculation for High-Throughput Data Updates

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Solution Overview

Problem

Conventional CRC processing circuits struggle to support high data throughput rates demanded by emerging wire transmission standards, such as 100 Gbps Ethernet, due to inefficiencies in recalculating CRC values when only a small portion of the data is modified.

Innovation Solution

The method involves dividing data into blocks of fixed size equal to the degree of a generator polynomial, performing independent CRC computations for each block in parallel, and combining these using an XOR operation, with the option to access pre-calculated CRCs from lookup tables and stopping computations when a loop condition is met.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional CRC processing circuits recalculate CRC values for the entire payload, then error detection accuracy is maintained, but processing speed and throughput are insufficient for high-speed transmission standards

Engineering Contradiction:

ImproveCRC processing throughputVSAvoidCRC recalculation time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent divides the payload into multiple fixed-size blocks, each processed independently through separate CRC computation circuits. This segmentation enables parallel processing of multiple blocks simultaneously, dramatically increasing throughput while maintaining error detection accuracy through XOR combination of individual block CRCs

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent pre-calculates and stores CRC values for all possible 8-bit data values in lookup tables during system initialization. This preliminary action allows the processing circuit to quickly retrieve pre-computed CRCs during runtime without performing full polynomial division, significantly reducing processing time while maintaining accuracy

Inventive Principle:

Principle #10Preliminary action

2Reliability

If full payload CRC recalculation is performed after data modification, then error detection reliability is ensured, but processing latency increases for high-speed networks

Engineering Contradiction:

Improveerror detection accuracyVSAvoidCRC computation duration

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent extracts only the modified blocks from the payload after data changes occur, applying CRC computation exclusively to these extracted blocks rather than recalculating for the entire payload. This selective approach maintains error detection reliability through XOR combination with unchanged block CRCs while dramatically reducing computation duration

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs partial CRC computation by calculating CRCs for only the necessary number of blocks required to cover the modified data region, rather than computing CRCs for all blocks in the payload. This partial action reduces processing time while maintaining sufficient error detection coverage through strategic block selection

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS10248498B2Cyclic redundancy check calculation for multiple blocks of a message

Publication Date: 2019.04.02 FUTUREWEI TECHNOLOGIES INC

AI summary

The disclosure relates to technology performing a cyclic redundancy check (CRC). Data is divided into a plurality of blocks, each of the plurality of blocks having a fixed size equal to a degree of a generator polynomial. A CRC computation is independently performed on each of the plurality of blocks, and the CRC computation for each of the plurality of blocks is combined by application of an exclusive or (XOR) operation.