Parallel CRC Digest Circuit for High-Speed SSD Testing
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Solution Overview
Problem
Conventional systems for determining cyclic redundancy checks (CRCs) in SSD testing are undesirably slow, which hampers the ability of SSD Automated Test Environment (ATE) systems to operate at the maximum transfer rate of SSDs, especially when dealing with large data packets.
Innovation Solution
The implementation of a fast parallel CRC determination system that generates a CRC value for a 256-bit input packet in one clock cycle, utilizing a pipelined digest circuit with multiple first and second circuits performing digest functions equivalent to shifting through a linear feedback shift register (LFSR), and an XOR circuit to produce the word digest, allowing for parallel processing of subwords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sequential CRC determination methods are used, then the system is simple to implement, but the processing speed is too slow to support high-rate SSD testing
Solution Approach 1:
The patent divides the 256-bit input packet into multiple subwords (e.g., eight 32-bit subwords). Each subword is processed independently by separate first circuits in parallel to generate subword digests. This segmentation enables simultaneous processing of multiple data segments, dramatically increasing CRC calculation speed while keeping individual circuit components relatively simple.
Solution Approach 2:
The patent transitions from sequential processing (single dimension in time) to parallel processing (adding a spatial dimension by processing multiple subwords simultaneously). The pipelined digest circuit structure allows multiple stages of processing to occur concurrently, effectively utilizing the time dimension to achieve high-speed operation without proportionally increasing overall system complexity.
2Productivity
If parallel processing is implemented to increase CRC calculation speed, then processing throughput increases, but the device complexity increases
Solution Approach 1:
The testing process is segmented into distinct phases: subword digest generation, second digest calculation, and final CRC assembly. Each phase is handled by dedicated circuit blocks that operate in parallel on different data segments. This segmentation allows high productivity through parallelism while managing complexity by organizing circuits into functional modules.
Solution Approach 2:
The first circuits perform preliminary digest calculations on subwords in parallel before the main CRC assembly stage. This preliminary action prepares intermediate results that are then combined in subsequent stages, enabling the system to achieve high throughput by pre-processing data segments concurrently rather than sequentially.
3Speed
If fast parallel CRC determination is implemented, then SSD testing can operate at maximum transfer rate, but the system requires complex pipelined digest circuits
Solution Approach 1:
The patent implements a dynamic pipelined digest circuit where data flows through multiple processing stages in a coordinated manner. The circuit adapts its operation to process different subword positions at different pipeline stages, with each stage optimized for specific processing tasks. This dynamic structure enables maximum testing rates by keeping all circuit resources actively engaged in parallel processing operations.
Solution Approach 2:
The pipelined digest circuit is segmented into distinct functional stages: subword digest generation circuits, second digest calculation circuits, and final XOR assembly circuits. Each segment handles specific processing tasks independently but coordinates with other segments through the pipeline, enabling high-speed operation while managing complexity through functional decomposition.
Data Source
AI summary
Fast parallel CRC determination to support SSD testing includes a test data pattern generator for generating test data for storage onto a memory storage device under test (DUT), wherein the generator is operable to generate, every clock cycle, a respective N bit word comprising a plurality of M bit subwords, a digest circuit operable to employ a digest function on each N bit word to produce, every clock cycle, a respective word digest for each N bit word, and a storage circuit operable to store each N bit word along with an associated word digest to the DUT. The digest circuit includes a plurality of first circuits each operable to perform a first digest function on a respective subword of the plurality of subwords, in parallel, to produce a plurality of subword digests, a plurality of second circuits each operable to perform a second digest function on a respective subword digest of the plurality of subword digests, the second digest function being equivalent to shifting the respective subword digest through a linear feedback shift register (LFSR) then followed by (I×M) zero bits, wherein I is related to a word position, within the N bit word, of a respective subword that generated the respective subword digest, and an XOR circuit operable to XOR outputs of the plurality of second circuits together along with a shifted prior LFSR state to produce the word digest of the N bit word.