Parallel CRC Pipeline for High-Rate Multi-Frame Ethernet Packets
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Solution Overview
Problem
Conventional cyclic redundancy check (CRC) calculations for multi-frame Ethernet packets are inefficient, particularly at high data transmission rates, due to the complexity and time required for calculating CRC values across multiple frames.
Innovation Solution
A pipelined processing mechanism with multiple stages is employed to calculate CRC values in parallel, utilizing zero-wheeling blocks to convert CRC values and XOR operations for efficient combination into a final CRC value, allowing for faster calculation by processing CRC value portions in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sequential CRC calculation is used for multi-frame packets, then calculation accuracy is maintained, but calculation speed becomes insufficient at high data transmission rates
Solution Approach 1:
The patent divides the multi-frame packet into individual frame units, each processed by separate CRC calculation circuits. Each frame's CRC is calculated independently and simultaneously in parallel, rather than sequentially processing frames one after another. This segmentation enables multiple CRC calculations to occur concurrently, dramatically improving overall calculation speed for multi-frame packets.
Solution Approach 2:
The patent transitions from sequential (one-dimensional) CRC calculation to parallel (multi-dimensional) processing by implementing multiple CRC calculation circuits that operate simultaneously. The pipelined architecture creates multiple processing stages that can handle different frames at different times, effectively adding temporal and spatial dimensions to the calculation process, thereby increasing throughput without sacrificing accuracy.
2Productivity
If parallel processing is implemented for CRC calculation, then calculation speed improves, but device complexity increases
Solution Approach 1:
The patent employs universal zero-wheeling circuits that can be applied to any CRC value regardless of which frame it comes from. These circuits perform the same mathematical operation (multiplication by powers of two modulo the generator polynomial) on all intermediate CRC values. This universality allows the same circuit design to be reused across multiple processing paths, reducing overall complexity compared to having specialized circuits for each frame.
Solution Approach 2:
The patent pre-calculates and stores the powers of two modulo the generator polynomial in lookup tables before actual CRC processing begins. During parallel CRC calculation, the zero-wheeling operation simply retrieves pre-computed values and applies them through XOR operations, rather than performing complex modular multiplication in real-time. This preliminary preparation significantly reduces the computational complexity during the actual parallel processing phase.
Data Source
AI summary
Techniques for calculation of CRC values for very large Ethernet packets in a quick manner are disclosed. Portions of CRC values are calculated each frame and are combined to arrive at a final CRC value for the frame. The CRC values for each frame are also combined to arrive at the final value for the packet. The use of the zero-wheeling function allows for each CRC value calculation to be a calculation of a limited set of data (e.g., one chunk of a frame), which allows such calculations to be completed quickly.