Parallel CRC Generation for High-Rate Image Data Streams
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Solution Overview
Problem
As image sensors produce higher resolution images and operate at faster clock rates, existing Cyclic Redundancy Check (CRC) value determination schemes struggle to efficiently handle the increasing amount of image data at higher data rates, necessitating improved methods for error detection in electronic devices like cameras and computers.
Innovation Solution
The implementation of parallelized CRC computation using pre-computed CRC values, where the input data stream is split into multiple parallel streams, allowing each CRC generator to compute CRC values in parallel and access stored transformation values for efficient CRC determination, thereby maintaining high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sequential CRC computation is used, then storage requirements are minimized, but computation speed cannot keep up with increasing data rates and resolutions
Solution Approach 1:
The input data stream is divided into multiple parallel sub-streams, each processed by a separate CRC generator. This segmentation allows simultaneous computation of multiple CRC values, increasing overall processing speed and throughput to match higher data rates and resolutions while maintaining manageable storage requirements for pre-computed tables.
Solution Approach 2:
The patent transitions from sequential single-dimensional processing to parallel multi-dimensional processing by distributing data across multiple CRC generators operating simultaneously. This dimensional expansion in processing architecture enables the system to handle increased data volumes and higher resolutions without proportionally increasing storage requirements.
2Productivity
If parallelized CRC computation is implemented, then throughput increases to handle higher data rates, but device complexity increases
Solution Approach 1:
Multiple CRC generators are designed with identical universal architecture and functionality, each capable of processing data sub-streams independently using the same pre-computed transformation values. This universality simplifies the overall system design by repeating a standardized module rather than creating complex unique processors for each parallel stream.
Solution Approach 2:
CRC transformation values are pre-computed and stored in lookup tables before runtime processing. This preliminary action allows the parallel CRC generators to perform rapid computations by retrieving pre-calculated values rather than performing complex calculations in real-time, thereby increasing throughput without proportionally increasing computational complexity.
3Measurement precision
If more pre-computed CRC values are stored, then computation accuracy is improved, but storage requirements increase
Solution Approach 1:
The patent uses a limited set of pre-computed transformation values that are sufficient for accurate CRC computation across all parallel streams. Rather than storing exhaustive CRC values for every possible data combination, the system stores a optimized subset that provides the necessary precision for error detection while minimizing storage requirements.
Solution Approach 2:
The system changes the parameter of pre-computed values from storing complete CRC results to storing transformation values that can be applied to data sub-streams. This parameter transformation reduces the storage footprint while maintaining computational accuracy, as the transformation values are more compact and can be reused across multiple parallel processing paths.
Data Source
AI summary
A system such as an imaging system may include Cyclic Redundancy Check (CRC) value generation circuitry. The CRC value generation circuitry may include a data splitter that splits an input data bit stream instead multiple split data bit streams each inserted with a number of bits having a value of 0. A plurality of CRC value generators may each have a corresponding input path to receive a respective one of the split data bit streams and generate corresponding partial CRC values. A data combiner coupled to the plurality of Cyclic Redundancy Check value generators may combine the partial CRC values to generate a final CRC value. A normalizer may be coupled between each of the plurality of CRC generators and the data combiner. Two CRC value data storage structures may help the plurality of Cyclic Redundancy Check value generators and the data combiner perform the desired CRC computations.


