Parallel CRC Circuit Using LUT Alignment to Cut Routing Latency
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Solution Overview
Problem
Current CRC computation methods are inefficient for parallel processing due to complex routing requirements and high latency, especially when using generator polynomials and shift registers, which hinder effective error detection in communication standards.
Innovation Solution
A method utilizing Look-Up Tables (LUTs) to align input bit sequences with CRC generator matrices, allowing parallel processors to perform CRC computations without complex routing, thereby reducing processing steps and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex routing and permutation networks are used to align input bits with generator matrix rows, then CRC computation accuracy is maintained, but processing latency and device complexity increase
Solution Approach 1:
The patent pre-organizes the generator matrix rows in a specific order within the LUT and pre-aligns input bit sequences before processing. This preliminary arrangement eliminates the need for complex permutation networks during actual CRC computation, reducing latency while maintaining accuracy
Solution Approach 2:
The patent extracts and removes the complex routing and permutation network components from the CRC computation system. By using a simplified LUT-based approach with pre-aligned inputs, it achieves the same computational accuracy without the time-consuming complex routing infrastructure
2Measurement precision
If complex routing and permutation networks are used to align input bits with generator matrix rows, then CRC computation accuracy is maintained, but device complexity increases
Solution Approach 1:
The patent removes complex routing and permutation networks from the system by using a simplified LUT-based approach where generator matrix rows are stored in a predetermined order, eliminating the need for complex switching and routing infrastructure
Solution Approach 2:
The patent uses a LUT that stores copies of generator matrix rows in a specific arrangement, allowing direct access without complex routing. The LUT acts as a simplified copy-based storage mechanism that replaces the need for dynamic permutation networks
3Ease of manufacture
If traditional sequential CRC computation methods are used, then implementation simplicity is maintained, but processing speed decreases
Solution Approach 1:
The patent segments the input bit sequence into multiple parallel streams that can be processed simultaneously using multiple LUTs and parallel processors. This segmentation enables parallel computation while maintaining the simplicity of the basic LUT-based approach
Solution Approach 2:
The patent transitions from sequential single-processor CRC computation to parallel multi-processor computation by organizing data in dimensional structures that allow simultaneous processing across multiple units, thereby increasing throughput while keeping individual processor logic simple
Data Source
AI summary
A cyclic redundancy check, CRC, computation circuit comprising an input for receiving an input stream having an input bit sequence comprising two or more bits at a time aligned to rows of a CRC generator matrix stored in a Look Up Table, LUT; a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT comprises a plurality of addresses wherein at least one of the addresses is configured to store two or more rows of the CRC generator matrix; and the set of parallel processors is configured to: combine LUT data with the input stream by using two or more bits of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT; and combine generated two or more intermediate parity bit sequences into a single parity bit sequence.