Parallel CRC Error Checking for Soft-Error Correction in Memory Arrays
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Solution Overview
Problem
Programmable integrated circuits face inefficiencies in detecting and correcting soft errors caused by radiation-induced changes in configuration random-access-memory cells, leading to time-consuming error checking processes and frequent disruptions when reloading configuration data.
Innovation Solution
The integration of multiple row cyclic redundancy check (CRC) circuits and an array CRC circuit with pipeline registers and multiplexing circuits for efficient error detection and correction, allowing for parallel processing and reduced computational time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sequential CRC error checking is used, then the error detection capability is provided, but the error checking time is excessively long (requiring several million clock cycles for 100 million CRAM cells)
Solution Approach 1:
The patent divides the large array of CRAM cells into multiple rows, with each row processed by a separate CRC circuit. This segmentation allows parallel error checking across all rows simultaneously, reducing the total checking time from several million clock cycles to a fraction of that time while maintaining comprehensive error detection coverage.
Solution Approach 2:
The patent transitions from sequential one-dimensional error checking to parallel multi-dimensional processing by implementing multiple CRC circuits that operate simultaneously on different rows. This dimensional expansion from single-thread sequential processing to multi-thread parallel processing dramatically accelerates error checking throughput.
2Reliability
If the entire programmable device is reloaded every time a soft error is detected, then error correction is achieved, but unnecessary frequent disruptions and significant power consumption occur
Solution Approach 1:
The patent extracts and identifies the specific row containing the error using individual CRC circuits for each row. By pinpointing the exact location of the soft error at the row level, the system can selectively reload only the affected row's configuration data rather than reloading the entire device, thereby reducing disruptions and power consumption while maintaining reliability.
Solution Approach 2:
The patent introduces row-level CRC circuits as intermediaries between the CRAM cell array and the reload mechanism. These intermediary circuits provide granular error detection at the row level, enabling targeted error correction actions that avoid the overhead of full-device reloads.
3Productivity
If multiple row CRC circuits and array CRC circuit are implemented for parallel processing, then error checking speed is significantly improved, but circuit complexity increases
Solution Approach 1:
The patent implements CRC circuits that serve dual purposes: individual row CRC circuits both detect errors in their respective rows and contribute to the overall array error detection. This multi-functionality allows the system to achieve parallel processing speedups without proportionally increasing the total circuit complexity, as each circuit component performs multiple roles in the error detection hierarchy.
Data Source
AI summary
Integrated circuits with a memory array may include error checking circuitry for detecting, locating, and correcting soft errors in the memory array. The error checking circuitry may include row cyclic-redundancy-check (CRC) circuits each of which is operable to receive bits from respective groups of memory elements in the array and may also include an array CRC circuit. In one embodiment, the row CRC circuits compute CRC values based on bits stored in each of the memory elements in the respective groups of memory without the use of the array CRC circuit. After all of the columns have been read out, the array CRC circuit may be used to combine the CRC values from the different row CRC circuits. In another embodiment, the array CRC circuit may update the array CRC value each time the row CRC circuits update their CRC values in response to selecting a new column for readout.