Parallel CRC Computation Reconfiguration for Multi-Protocol Data Blocks
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Solution Overview
Problem
Existing error detection code computation methods in telecommunications networks lack configurability to adapt to various protocols and varying data block sizes, limiting their effectiveness as network usage grows and new protocols emerge.
Innovation Solution
A reconfigurable apparatus with parallel computation means and a configurator that can implement different CRC error detection methodologies, using a matrix-based configuration to determine the required setup for computing CRC error detection codes, allowing for flexible adaptation to diverse protocols and data sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed CRC computation apparatus is used, then the computation speed is high, but the adaptability to different protocols and data block sizes is poor
Solution Approach 1:
The patent implements a reconfigurable CRC computation apparatus where the computation structure can be dynamically changed through configuration data. The apparatus transitions from a fixed structure to a dynamic one that can be adapted to different CRC methodologies and data block sizes by loading appropriate configuration parameters, thereby resolving the contradiction between fixed-speed computation and protocol adaptability.
Solution Approach 2:
The patent changes the parameters of the computation apparatus by introducing configuration data that defines the computation structure. By varying parameters such as the CRC polynomial degree and data block size through configuration, the apparatus can adapt to different protocols without changing its physical structure, thus maintaining computational efficiency while achieving versatility.
2Productivity
If parallel computation is used to improve computation speed, then the processing capacity increases, but the configurability for different methodologies decreases
Solution Approach 1:
The patent creates a universal CRC computation apparatus that can perform multiple CRC methodologies through parallel computation structures. The apparatus is designed with configurable parallel computation units that can be arranged in different configurations depending on the required CRC methodology, allowing it to maintain high computation speed while supporting multiple protocols and methodologies simultaneously.
3Adaptability or versatility
If the apparatus is configured to support multiple CRC methodologies, then the protocol coverage is maximized, but the device complexity increases
Solution Approach 1:
The patent segments the CRC computation apparatus into configurable modules that can be independently configured for different methodologies. By dividing the computation structure into separable units that can be arranged in different configurations, the apparatus achieves comprehensive protocol coverage without proportionally increasing overall device complexity, as the same physical resources are reused across different protocol configurations.
Data Source
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AI summary
An apparatus (1) for implementing a cyclic redundancy check (CRC) error detection methodology to compute a CRC error detection code for data according to the methodology, comprising computation means (2) which uses parallel computation (4) to compute the CRC error detection code, and configurator means (3) which uses the CRC error detection methodology to determine a configuration of the computation means required to compute the CRC error detection code, and configures (25) the computation means accordingly, wherein the configurator means is able to use each of a plurality of CRC error detection methodologies to determine a configuration of the computation means required for parallel computation of a CRC error detection code according to each of the methodologies, and the computation means is configurable to allow configuration thereof for parallel computation of each CRC error detection code.