Parallel CRC Circuit Layout for Low-Latency Packet Error Detection
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Solution Overview
Problem
Existing error detection techniques using cyclic redundancy check (CRC) functions in communication devices are not effective in detecting errors caused by noise and interference during data transmission, particularly in high-speed networks where latency is a concern.
Innovation Solution
A communication device with multiple CRC circuits arranged in parallel, each processing a portion of the incoming packet segment and an initial value, allowing for efficient computation of CRC values to detect errors in data units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single CRC circuit is used for error detection, then the device complexity is low, but the error detection effectiveness and speed are insufficient for high-speed networks
Solution Approach 1:
The incoming packet is divided into multiple segments, with each segment processed by a dedicated CRC circuit in parallel. This segmentation allows the system to maintain high reliability through multiple independent error detection paths while managing device complexity by distributing the computational load across identical modular units.
Solution Approach 2:
The patent transitions from sequential single-circuit processing to parallel multi-circuit processing, adding a dimensional aspect to the error detection system. By arranging CRC circuits in parallel rather than series, the system achieves both improved reliability and maintained complexity through spatial distribution of computational tasks.
2Loss of time
If a single CRC circuit processes the entire packet sequentially, then the device complexity is low, but the processing latency increases in high-speed networks
Solution Approach 1:
The packet processing task is segmented into multiple parallel streams, each handled by a dedicated CRC circuit. This segmentation eliminates the sequential bottleneck, reducing processing latency by allowing simultaneous error detection across different packet segments while keeping each individual circuit simple and manageable.
Solution Approach 2:
Multiple CRC circuits operate continuously and simultaneously on different packet segments, ensuring that error detection proceeds without idle waiting time. This continuous parallel operation reduces latency by eliminating the sequential gaps that would occur in single-circuit processing, while the modular nature keeps device complexity controlled.
3Productivity
If multiple CRC circuits process different packet segments in parallel, then the error detection speed and effectiveness improve, but the device complexity increases
Solution Approach 1:
The packet detection task is divided into segments processed by multiple identical CRC circuits working in parallel. This segmentation increases productivity by enabling simultaneous error detection across multiple segments, while the use of identical modular circuits rather than complex heterogeneous systems helps control the increase in device complexity.
4Adaptability or versatility
If traditional sequential CRC processing is used, then the device structure is simple, but it cannot effectively handle varying packet lengths in high-speed networks
Solution Approach 1:
The packet is segmented into fixed-size portions that can be uniformly processed by identical CRC circuits regardless of the original packet length. This segmentation approach provides adaptability to varying packet lengths by normalizing the input data into consistent segments, while the simplicity of identical processing circuits maintains manageable device complexity.
Data Source
AI summary
A communication device and associated method is provided. The communication device includes: a controller; a packet buffer, configured to store a current packet segment and a previous packet segment of an incoming packet; and a plurality of cyclic redundancy check (CRC) circuits, wherein each CRC circuit is individually fed with a portion of the current packet segment and/or a portion of the previous packet segment in a respective cycle of the incoming packet, and an initial value, wherein the plurality of CRC circuits are arranged in parallel.