Programmable Parallel CRC Circuit for Multi-Polynomial Throughput
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Solution Overview
Problem
Current CRC systems face limitations due to non-standardized generator polynomials and restricted throughput, particularly in hardware implementations, which restrict the use of CRC hardware accelerators for data consistency checks, often requiring serial calculations and limited polynomial support.
Innovation Solution
A programmable circuitry system that generates parallel CRC signature bits using a programmable polynomial decoder and multiplexors, enabling CRC signature generation in a single clock pulse, accommodating different polynomial schemes and supporting various data protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial shift register implementation is used, then polynomial support is limited and device complexity is reduced, but throughput is severely restricted and calculation time increases
Solution Approach 1:
The circuit divides the CRC calculation into multiple parallel segments, each handling a portion of the polynomial calculation. Multiple XOR gates and multiplexors are arranged in parallel stages to simultaneously process different bits of the input data, enabling parallel computation of CRC signature bits rather than sequential processing
Solution Approach 2:
The patent transitions from serial time-domain processing to parallel space-domain processing by introducing multiple simultaneous calculation paths. The circuit uses multiple XOR gates, multiplexors, and feedback paths that operate concurrently to generate all CRC signature bits in a single clock cycle, effectively moving from 1D sequential processing to 2D parallel processing architecture
2Adaptability or versatility
If programmable polynomial support is implemented, then adaptability to different protocols is improved, but device complexity and circuit requirements increase
Solution Approach 1:
The circuit implements a universal CRC generator that can support multiple different generator polynomials through programmable control. The multiplexors are configured to selectively connect different feedback paths based on the desired polynomial, allowing the same hardware circuit to adapt to various protocols (USB, PCIe, Ethernet, etc.) without requiring separate dedicated circuits for each polynomial type
Solution Approach 2:
The circuit pre-configures multiple polynomial feedback paths using multiplexors that can be programmed before operation. The selection logic and multiplexor configurations are established in advance to support different polynomials, enabling rapid switching between protocols without requiring dynamic reconfiguration during the actual CRC calculation process
Data Source
AI summary
Parallel CRC signature circuitry provides a plurality of modules in which a byte of parallel input data is receivable by each module. Each module includes a parallel data input for receiving a byte of parallel input data. Three levels of multiplexors are coupled to the parallel data input. A decoder decodes a polynomial to selection data. The selection data selects the inputs passed by the three levels of multiplexors, and each of the modules generates one byte of the parallel CRC signature free of a clock signal.