Parallel CRC Receiver Architecture for High-Speed Serial Packets
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Solution Overview
Problem
Conventional data parallelizing receivers face challenges in reducing latency and circuit complexity as the number of input bits increases, particularly in high-speed data transmission systems, due to the need for numerous XOR gates in CRC calculations, which delays the command input and processing.
Innovation Solution
A data parallelizing receiver that aligns previously and subsequently input bitstreams with clock signals of different phases, performs partial CRC calculations, and merges these results to adaptively detect data errors, reducing the number of XOR gates required and thus shortening error detection time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of input bits to be parallelized is increased to achieve high data rate, then the data transmission speed is improved, but the time taken to perform data error correction process increases
Solution Approach 1:
The patent divides the parallelized data into multiple sub-groups and performs CRC calculation on each sub-group separately using dedicated calculators. This segmentation allows simultaneous processing of multiple data portions, reducing the total error correction time despite increased parallelization degree.
Solution Approach 2:
The patent performs preliminary alignment of bitstreams with clock signals of different phases before CRC calculation. This preliminary organization of data into properly timed groups enables more efficient parallel processing and reduces the overall error correction time.
2Speed
If the number of input bits to be parallelized is increased to achieve high data rate, then the data transmission speed is improved, but the circuit complexity increases
Solution Approach 1:
The patent segments the complex CRC calculation task into multiple smaller sub-calculations performed by separate calculators on different data sub-groups. This segmentation distributes the circuit complexity across multiple simpler, identical modules rather than requiring one complex calculator, making the overall circuit more manageable and scalable.
Solution Approach 2:
The patent introduces a time dimension by using clock signals with different phases to organize and process parallelized data. This temporal dimension allows the system to handle increased data width without proportionally increasing spatial circuit complexity, as data is organized and processed across multiple clock phases.
3Speed
If conventional CRC calculation method is used with increased parallelization, then data rate is improved, but additional delay components are required
Solution Approach 1:
The patent performs preliminary alignment of incoming bitstreams with clock signals of different phases before the CRC calculation stage. This preliminary timing organization ensures that data is properly synchronized and grouped, eliminating the need for additional delay components that would otherwise be required during or after the CRC calculation process.
Data Source
AI summary
Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.