Interleaved Parallel CRC for 4-Bit SD Memory Bus Data
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Solution Overview
Problem
Current methods for communicating with Secure Digital (SD) memory cards in 4-bit mode require inefficient unpacking and repacking of data for CRC calculations, leading to excessive processing overhead and the need for specialized hardware, which is costly and not suitable for cost-sensitive applications.
Innovation Solution
A mechanism for interleaved parallel CRC calculation using a 64-bit accumulator and an interleaved parallel CRC table allows CRC calculations to be performed directly on SD bus data in its natural order, eliminating the need for data unpacking and repacking, and enabling efficient software-based CRC operations without specialized hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CRC calculation is used for 4-bit SD mode, then CRC error checking can be performed, but excessive processing overhead is incurred due to unpacking and repacking operations
Solution Approach 1:
The invention segments the 4-bit SD bus data into four separate 1-bit streams, each processed independently through its own CRC calculation pipeline. This segmentation allows parallel processing of multiple data lines simultaneously, eliminating the need for sequential unpacking and repacking operations while maintaining CRC error checking capability.
Solution Approach 2:
The invention transitions from conventional single-stream CRC processing to multi-dimensional parallel processing by introducing four independent CRC calculation paths for the four SD bus lines. This dimensional expansion allows the system to process all four data lines concurrently, dramatically reducing processing overhead while preserving reliability.
2Productivity
If specialized hardware is used for CRC calculation in 4-bit mode, then processing efficiency is improved, but system cost and complexity increase
Solution Approach 1:
The invention creates a universal CRC processing architecture that can handle both 1-bit and 4-bit SD modes through the same software-based mechanism. By making the CRC calculation system multi-functional and mode-agnostic, specialized hardware becomes unnecessary, reducing system complexity and cost while maintaining high processing efficiency through optimized software implementation.
Solution Approach 2:
The invention uses software-based CRC calculation that replicates the functionality of hardware CRC units through programmed operations. By copying the essential CRC calculation logic into software form, the system achieves hardware-like efficiency without requiring actual hardware implementations, thereby reducing device complexity and cost.
3Ease of manufacture
If 1-bit SPI mode is used for SD communication, then software-based CRC calculation becomes feasible, but bandwidth is reduced to 25% of theoretical maximum
Solution Approach 1:
The invention merges four separate 1-bit CRC calculation streams into a unified 4-bit parallel processing architecture. By combining the processing capabilities for all four SD bus lines into a single integrated software-based system, the invention achieves both the ease of software implementation and the high bandwidth of 4-bit mode, eliminating the need to choose between the two extremes.
Data Source
AI summary
In one embodiment, a mechanism for interleaved parallel cyclic redundancy check calculation for memory devices is disclosed. In one embodiment, a method includes generating an index value as part of a cyclic redundancy check (CRC) operation, the index value being a result of a first exclusive-or operation applied to both of input data directly as-is from a data bus and to data in a 64-bit accumulator utilized to store results of the CRC operation. The method also includes indexing an interleaved parallel CRC table with the index value to retrieve a 64-bit polynomial entry from the CRC table, performing a second exclusive-or operation on the retrieved polynomial entry and data in the 64-bit accumulator, storing the results of the second exclusive-or operation in the 64-bit accumulator, and transmitting contents of the 64-bit accumulator directly as-is to the data bus.