Parallel CRC Circuit for Single-Clock Multi-Bit Calculation
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Solution Overview
Problem
Traditional CRC calculation methods require multiple clock periods for inputting multi-bit information codes, leading to redundant calculation time and inefficiency.
Innovation Solution
A cyclic redundancy check circuit and method that utilize a configuration component to acquire configuration information and determine a generator polynomial, a CRC control component to output a clock signal and coefficients, and a parallel iteration component to perform parallel iteration of the information field, allowing for efficient CRC calculation with a single clock period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional serial shift circuit is used for CRC calculation, then the circuit structure is simple, but the calculation time increases linearly with the number of bits to be processed
Solution Approach 1:
The patent segments the information field into multiple bit groups (e.g., 4-bit groups) and processes each group in parallel using separate calculation paths. Each path handles one bit group simultaneously, dividing the original sequential processing task into parallel sub-tasks that can be executed concurrently, thereby reducing total calculation time while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The patent transitions from one-dimensional sequential processing (one bit at a time) to two-dimensional parallel processing by introducing a bit-group dimension. Multiple bit groups are processed simultaneously across different calculation paths, effectively adding a parallelism dimension to the CRC calculation architecture, which reduces calculation time from O(n) to O(n/k) where k is the number of parallel paths
2Ease of manufacture
If multi-bit information codes are input sequentially, then the circuit implementation is straightforward, but redundant calculation time is incurred
Solution Approach 1:
The patent merges multiple CRC calculation operations into a single clock cycle by combining parallel calculation paths that process different bit groups simultaneously. The merged architecture uses shared resources (such as the generator polynomial coefficients and XOR logic) across parallel paths, achieving both high productivity through parallelism and ease of manufacture through resource sharing and modular design
Solution Approach 2:
The patent performs preliminary organization of the information field into fixed-size bit groups before processing. This preliminary segmentation allows the circuit to immediately begin parallel processing without sequential overhead, and the pre-arranged group structure enables direct mapping to parallel calculation paths, improving productivity while keeping the implementation straightforward through systematic data preparation
Data Source
AI summary
Provided are a Cyclic Redundancy Check (CRC) circuit, and a method and an apparatus thereof, a chip and an electronic device, which belong to the technical field of computers. Herein, the cyclic redundancy check circuit may include: a configuration module configured to acquire configuration information and an information field, a CRC arbitration module configured to determine a generator polynomial according to the configuration information, a CRC control module configured to respond to triggering of the CRC arbitration module and output a clock signal, a coefficient corresponding to each power in the generator polynomial and the information field, a parallel iteration module configured to respond to the clock signal and implement parallel iteration for the information field according to the coefficient corresponding to the each power in the generator polynomial, as to output an iteration result, and a CRC output module configured to package the information field according to the iteration result.