Parallel CRC Residue Circuit Using Subblock Initial Values
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Solution Overview
Problem
Conventional CRC calculating circuits face significant processing delays and increased circuit scale due to memory requirements for partial CRC codes, especially when used with parallel turbo decoders, and require additional multiplying and residue circuits.
Innovation Solution
A parallel residue operator that divides input data into subblocks and uses initial value generating sections to calculate partial residues, followed by a logic section for logical operations and a cumulative adding section to reduce processing delay without the need for additional multiplication or residue circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CRC calculating circuits use memory to store all partial CRC codes for parallel processing, then parallel processing capability is improved, but circuit scale increases and processing delay increases
Solution Approach 1:
The patent divides input data into multiple subblocks and processes each subblock independently through separate CRC calculating circuits. Each circuit handles a specific portion of the data in parallel, eliminating the need to store all partial CRC codes in memory. The segmentation of data processing paths allows high-speed parallel computation while maintaining a compact circuit structure without large memory requirements.
Solution Approach 2:
The patent pre-calculates and stores only the initial values for the CRC calculating circuits before parallel processing begins. These preliminary computed values are held in small registers, and the actual parallel computation proceeds without requiring memory storage of intermediate results. This preliminary action enables parallel processing while minimizing memory usage and circuit complexity.
2Measurement precision
If conventional CRC calculating circuits store partial CRC codes in memory, then calculation accuracy is maintained, but processing delay increases
Solution Approach 1:
By segmenting the input data into subblocks and processing each segment independently through dedicated CRC circuits, the patent achieves parallel computation that maintains full calculation accuracy for each segment. The segmented approach eliminates sequential processing delays while preserving the mathematical integrity of CRC calculations through independent parallel paths.
Solution Approach 2:
The patent implements continuous parallel computation across multiple CRC calculating circuits that operate simultaneously on different data subblocks. This continuous useful action eliminates idle time and memory access delays, maintaining high calculation accuracy while achieving sustained high-speed processing without interruption or sequential bottlenecks.
3Productivity
If additional multiplying and residue circuits are added for parallel CRC calculation, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent merges the functions of multiple CRC calculating circuits into a unified parallel processing structure where circuits share common input data distribution and output combination logic. This merging approach achieves high processing speed through parallel computation while reducing overall device complexity by eliminating redundant components and optimizing the interconnection structure between circuits.
Solution Approach 2:
The patent designs universal CRC calculating circuits that can process different data subblocks using the same structural framework. Each circuit is multi-functional, handling both the CRC calculation and initial value management, which eliminates the need for separate specialized circuits for each function. This universality improves processing speed through parallelism while controlling device complexity by reusing identical circuit blocks.
Data Source
AI summary
A parallel residue arithmetic operation unit is provided to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit includes input terminals to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units for calculating logical multiplications of part CRC values, and a cumulative adding unit for cumulatively adding values output from the AND units.