Parallel CRC Encoding Using Transfer Matrices to Cut Clock Cycles
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Solution Overview
Problem
Current CRC encoding methods are inefficient as they can only process one input bit per clock, leading to high system overhead and low operation efficiency in large-scale systems.
Innovation Solution
The method involves mapping the CRC generator polynomial to generate an (r+1)-order transfer matrix, deleting a row and column to form an r-order transfer matrix, adding dummy bits to align with parallel operation width, and using zero input and state transfer matrices to calculate the CRC check sequence in parallel, reducing the clock cycles required for encoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a feedback shift register is used to implement CRC encoding, then the encoding can be performed using a standard division circuit, but only one input bit can be processed per clock cycle, resulting in high system overhead and low operation efficiency
Solution Approach 1:
The patent segments the input bit stream into multiple parallel channels, each processed by a dedicated sub-encoder. This allows N bits to be processed simultaneously in one clock cycle, transforming the serial processing limitation into parallel processing capability and thereby improving operation efficiency while maintaining the standard division circuit implementation approach
Solution Approach 2:
The patent introduces a parallel processing dimension by constructing multiple identical encoder circuits that operate simultaneously on different segments of the input data. This dimensional expansion from single-channel serial processing to multi-channel parallel processing resolves the contradiction between ease of manufacture and operation efficiency
2Device complexity
If a feedback shift register is used to implement CRC encoding, then the circuit structure is simple and easy to manufacture, but the system overhead is large and processing speed is slow
Solution Approach 1:
The patent merges multiple identical encoder circuits into a single parallel processing system. By combining N simple encoder circuits to process N bits simultaneously, the system achieves high processing speed while each individual circuit remains simple and easy to manufacture, thus resolving the contradiction between device complexity and processing speed
3Productivity
If parallel processing is implemented to process multiple bits per clock, then the system operation efficiency is improved, but the hardware overhead increases
Solution Approach 1:
The patent uses copying by creating N identical copies of the basic encoder circuit, each handling one bit of the parallel input. This approach allows the system to achieve high operation efficiency through parallel processing while keeping each individual circuit unit simple and reusable, thereby managing hardware overhead through replication of proven simple designs
Data Source
AI summary
The present invention discloses a method for fast cyclic redundancy check (CRC) encoding, and includes: mapping a CRC encoding generator polynomial to generate an (r+1)-order transfer matrix J; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix; forming a r×1 column matrix by first columns of 2nd to r+1th rows of said (r+1)-order transfer matrix; obtaining a zero input transfer matrix and a zero state transfer matrix of CRC encoding by the r-order transfer matrix and the r×1 column matrix; adding dummy bits before an input bit stream; and obtaining a CRC encoding check sequence according to the zero input transfer matrix, the zero state transfer matrix and the input bit stream after adding the dummy bits. The present invention further discloses an apparatus for fast cyclic redundancy check encoding.