Programmable Parallel Cryptographic Accelerator Using Butterfly Network
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Solution Overview
Problem
Conventional cryptographic algorithm acceleration methods are limited in their ability to accelerate multiple algorithms simultaneously due to a lack of integration of diffusion and confusion principles within the processing environment, leading to inefficient processing times and limited parallelization capabilities.
Innovation Solution
A programmable parallel computation and data manipulation system utilizing a butterfly network and lookup table to duplicate and permute data bits, allowing for simultaneous use of individual bits in multiple calculations, thereby integrating diffusion and confusion principles for accelerated cryptographic calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional systems maintain only one copy of each bit in a single location, then hardwired circuits can route multiple instances of values to combinational logic efficiently, but this limits general applicability to multiple algorithms and requires serial processing when bits are needed for multiple calculations
Solution Approach 1:
The patent creates multiple copies of each bit by replicating bit lines throughout the data processing system. Each bit is duplicated across multiple parallel bit lines, allowing the same bit value to be simultaneously accessed by different computational units for different algorithmic operations. This copying mechanism enables both high processing speed through parallel access and broad algorithm flexibility through programmable routing of the replicated bits.
Solution Approach 2:
The patent implements dynamic routing capabilities where the connections between replicated bit lines and computational units can be reconfigured based on the specific algorithm being executed. The system transitions from static hardwired connections to dynamic, programmable interconnections, allowing the same replicated bit structure to serve multiple algorithmic purposes by changing the routing configuration rather than the physical hardware.
2Productivity
If conventional systems maintain only one copy of each bit, then circuit routing is simplified, but additional software preparation is required for data input, slowing I/O processing
Solution Approach 1:
The patent performs preliminary duplication of bit data during the data input phase, creating multiple copies of each bit before the main computational process begins. This preliminary action eliminates the need for additional software preparation steps during I/O processing, as the bit replication infrastructure is already in place and ready for immediate use by the computational units, thereby reducing I/O processing time.
3Device complexity
If conventional systems use separate instructions for diffusion and confusion calculations, then implementation is simpler, but parallelization and pipe-lining potential are limited, increasing processing time
Solution Approach 1:
The patent merges the diffusion and confusion calculation instructions into a unified, integrated instruction set that can execute both operations simultaneously on the replicated bit lines. By combining what were previously separate sequential operations into a single parallel-executable instruction, the system achieves higher computational efficiency and better pipe-lining potential while maintaining relatively simple instruction set architecture through the use of a single programmable control mechanism.
Data Source
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AI summary
Methods and systems are provided for a programmable parallel computation and data manipulation accelerator that may be used, for example, in cryptographic calculations. They allow acceleration of a broad variety of cryptographic algorithms and/or portions of algorithms, and are not algorithm specific. This system comprises a butterfly and inverse butterfly multiplexing permuter network and a lookup table. This system may allow replication of input registers, "expansion," so that an individual bit may be used in multiple calculations in parallel, accelerating completion of the cryptographic algorithm. The system may allow "diffusion" of the expanded bits through the system's butterfly and inverse butterfly network, and may provide for "confusion" of the resulting bits through the system's lookup table. In some implementations, the system may allow completion of a computation within an algorithm within one clock cycle.