Parallel Cryptography Engine for High-Speed Data Encryption
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Solution Overview
Problem
Traditional hardware acceleration methods in cryptography toolkits like GmSSL perform symmetric encryption/decryption and digest calculations sequentially, leading to inefficiencies in speed and system performance.
Innovation Solution
A data encryption and decryption system that includes a host system, a sequencer, a hardware processor, direct memory access modules, and cryptography engines capable of parallel and chained calculations for symmetric encryption/decryption and digest algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If symmetric encryption/decryption and digest calculations are performed sequentially in traditional hardware acceleration methods, then the system structure is simple and easy to implement, but the encryption/decryption speed and system performance are low
Solution Approach 1:
The patent merges the symmetric encryption/decryption module and the digest calculation module into a single integrated hardware acceleration device. The symmetric encryption/decryption module and the digest calculation module share the same hardware resources and can operate in parallel, eliminating the need for sequential execution and improving overall processing speed.
Solution Approach 2:
The patent implements a dynamic control mechanism where the control unit can dynamically switch between different operation modes (encryption, decryption, digest calculation, or combined operations) based on the input commands. This dynamic flexibility allows the system to optimize performance for different operational scenarios while maintaining a unified hardware structure.
2Speed
If separate calculation modules are used for symmetric encryption and digest algorithms, then the modularity is high and maintenance is easy, but the processing speed is limited due to serial execution
Solution Approach 1:
The patent combines multiple calculation functions (symmetric encryption, decryption, and digest algorithms) into a single integrated module that can execute multiple operations simultaneously. The shared hardware resources include arithmetic logic units, data buffers, and control circuits that can be dynamically allocated to different functions based on operational requirements.
Solution Approach 2:
The integrated module is designed with universal functionality to perform multiple cryptographic operations. The same hardware resources can be configured to execute different algorithms (SM4, SM3, etc.) and different operation types (encryption, decryption, hashing) through software control, eliminating the need for separate dedicated hardware for each function.
Data Source
AI summary
A data encryption and decryption system a host system, sequencer, hardware processor, direct memory access modules, and cryptography engines having input and output buffers, and symmetric encryption/decryption and digest algorithm modules. The host system determines encryption/decryption calculation and/or digest calculation method, and generates corresponding encryption/decryption and/or digest calculation commands. The sequencer analyzes the encryption/decryption and/or digest calculation commands to generate control flow commands, and controls one or more of the direct memory access modules via the control flow commands to input data to be encrypted/decrypted into the input buffer of one or more cryptography engines. The hardware processor controls the symmetric encryption/decryption algorithm module to perform encryption/decryption calculations according to the encryption/decryption calculation commands, and/or, controls the digest algorithm module to perform digest calculations on data to be encrypted/decrypted according to the digest calculation commands, and sends calculation results to the host system by the direct memory access module.