Parallel Cryptographic and Hash Processing for Secure Boot Speed
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high-speed processing during secure boot operations due to the sequential nature of encryption, decryption, and hash computation processes, which can prolong processing time.
Innovation Solution
The semiconductor device architecture includes a cryptographic processing unit and a hash processing unit that perform computational processing and hash computation in parallel, with data transfer between these units via a direct path separate from the main bus, allowing for efficient matching of buffer capacities and timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hash operation is performed after decryption process sequentially, then verification accuracy is ensured, but processing time becomes long
Solution Approach 1:
The patent applies preliminary action by performing hash computation on decrypted data blocks immediately after decryption and before final verification completion. The hash processing unit calculates hash values for each decrypted block and stores them in advance, so that when verification is needed, the hash values are already prepared, eliminating the need to wait for sequential completion of all decryption and hashing operations.
Solution Approach 2:
The patent introduces parallel processing by adding a temporal dimension to the originally sequential process. Multiple operations (decryption of one block, hash computation of another block, verification preparation) occur simultaneously through parallel processing units, transforming the single-threaded sequential execution into multi-threaded concurrent execution, thereby reducing total processing time while maintaining verification accuracy.
2Productivity
If parallel processing is implemented for encryption and hash computation, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the hash processing unit to serve multiple functions: it computes hash values for decrypted data blocks, stores hash values in its buffer, and provides verification services. This multi-functional design reduces the need for separate dedicated components for each function, thereby limiting the increase in device complexity while enabling parallel processing to improve processing speed.
Solution Approach 2:
The patent uses the buffer of the hash processing unit as an intermediary component that mediates between the decryption unit and the verification process. The buffer temporarily stores decrypted data blocks and their corresponding hash values, allowing the decryption unit to continue processing while the verification unit retrieves data at its own pace, thus enabling parallel operation without requiring complex synchronization mechanisms.
Data Source
AI summary
To provide a semiconductor device and a control method for a semiconductor device that realizes high-speed processing. The semiconductor device includes a storage unit, an encryption processing unit, and a hash processing unit. The data stored in the storage unit is transferred to the encryption processing unit for each pre-calculation data of the first calculation unit, the encryption processing unit applies the calculation processing to generate post-calculation data. The generated first calculation unit of the post-calculation data is transferred to the hash processing unit, the hash processing unit applies the hash calculation process to the post-calculation data of the second calculation unit. The post-calculation data is transferred to the storage unit, and the calculation processing and the hash calculation processing are performed in parallel.