Parallel Current Adder Circuit for Binary Operand Summation
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Solution Overview
Problem
Conventional adder circuits for binary numbers become complex and require additional full adders as the number of bits increases, making them inefficient for higher bit binary number additions.
Innovation Solution
An adding circuit and method using current sources and switches in parallel configuration, where each switch corresponds to a bit in the binary operand, with current sources providing amperage values in binary progression, allowing for the direct computation and display of the sum through an ammeter or ADC circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional full adders are cascaded in series to add N-bit binary numbers, then the addition function is achieved, but the circuit complexity increases significantly as the number of bits increases
Solution Approach 1:
The patent segments the addition computation into parallel bit-position groups rather than sequential full adder stages. Each bit position j has its own dedicated current source and switch, allowing independent processing of all bit positions simultaneously rather than cascading through N stages of full adders.
Solution Approach 2:
The patent transitions from a temporal/cascaded dimension (where full adders process bits sequentially through carry propagation) to a spatial/parallel dimension (where all bit positions are handled simultaneously through parallel current sources and switches). This dimensional change enables O(1) complexity regardless of bit width N.
2Adaptability or versatility
If additional full adders are added to handle higher bit binary numbers, then the addition capability for higher bits is improved, but the overall circuit complexity and component quantity increase
Solution Approach 1:
The patent creates a universal addition structure where the same parallel current source and switch configuration works for all bit positions from 0 to N-1. A single set of M parallel branches handles all bit widths uniformly, eliminating the need to add separate full adder stages for higher bits while maintaining adaptability to any N-bit addition requirement.
3Speed
If conventional series-cascaded full adders are used, then the addition function is implemented, but the computation speed decreases as the number of bits increases due to carry propagation delay
Solution Approach 1:
The patent performs preliminary action by pre-configuring all current sources and switches for all bit positions before computation begins. Since all bit positions are ready simultaneously with their current sources and switches pre-connected in parallel, the addition computation can proceed instantly without waiting for carry propagation through sequential stages, achieving O(1) computation speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces circuit complexity and enables rapid computation of binary sums with fewer components, improving efficiency and speed compared to conventional systems.
Implementation Method 1
The current source (i,j) can send a direct current (i,j) through the switch (i,j) to the electrically conductive line through to the ammeter
Data Source
AI summary
An adding circuit, device and method for adding M binary operands/numbers. The binary operand (i) of the M binary operands has Ni bits. First, for i=1, . . . , M and j=1, . . . , Ni, the bit (i,j) is applied to a switch (i,j) that might be on if the bit (i,j) is 1, and off if the bit (i,j) is 0. Then a direct current (i,j) is sent through the switch (i,j), the direct current (i,j) having a value of (a) 2j−1 if the switch (i,j) is on, and (b) zero if the switch (i,j) is off. All the direct currents (i,j) with their self-summing capabilities are merged into a combined current on an electrically conductive line. An ammeter on the electrically conductive line displays the decimal value of the sum of the M binary operands.