Parallel DAC Double-Cascade Circuit for 50 GS/s Switching

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Solution Overview

Problem

Existing parallel digital-analog converters face limitations in achieving high sample rates due to the need for precise current weighting and the Miller effect, which restricts their use in high-bandwidth applications such as optical fiber systems, with most converters capped at around 22 GS/s.

Innovation Solution

The implementation of a double cascade circuit using transistors with constant current sources and bias voltage, allowing for continuous current supply and reducing the need for transistor switching, thereby enhancing switching speed and bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If current weighting is implemented to ensure accurate conversion, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:

Improveconversion accuracyVSAvoidconverter structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the fundamental operating parameter from weighted current switching to unweighted current mirror operation. By using a current mirror circuit where the intermediate storage cell controls the mirroring ratio rather than switching weighted currents, the converter achieves accurate conversion without complex weighting networks, thus improving manufacturing precision while reducing device complexity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical switching of weighted currents with an electronic current mirror mechanism. Instead of physically switching between different weighted current sources, the system uses transistor-based current mirroring controlled by the intermediate storage cell, simplifying the overall converter structure while maintaining conversion accuracy

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Speed

If higher reference current is used to improve switching speed, then speed is improved, but manufacturing precision deteriorates

Engineering Contradiction:

Improveswitching speedVSAvoidconversion accuracy

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent replaces the weighted current switching mechanism with a current mirror circuit. This substitution allows the use of higher reference currents to improve switching speed without compromising precision, because the current mirror inherently maintains accurate current ratios through transistor matching rather than relying on precise weighted current distribution

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the current distribution approach from weighted switching to unweighted mirroring. By using a single reference current that is mirrored rather than multiple weighted currents that must be precisely switched, the system can operate at higher speeds while maintaining manufacturing precision through transistor geometry control rather than complex current weighting

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If transistor switching is used for conversion, then device complexity is reduced, but frequency response deteriorates due to Miller effect

Engineering Contradiction:

Improveconverter structureVSAvoidsample rate

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent substitutes the transistor switching mechanism with a current mirror circuit controlled by the intermediate storage cell. This substitution eliminates the Miller effect associated with transistor switching, enabling higher sample rates and frequency responses while maintaining relatively simple device structure through the use of standard current mirror topology

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational mechanism from switching-based conversion to current mirror-based conversion. By using the intermediate storage cell to control current mirroring rather than transistor switching, the system achieves higher frequency responses and sample rates without increasing device complexity, as the current mirror circuit is inherently simpler than switched transistor networks

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7924196B2Digital-analog converter

Publication Date: 2011.04.12 IHP GMBH INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS LEIBNIZ INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK

AI summary

A parallel digital-analog converter for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters (200) which respectively include an intermediate storage cell (202) and a current cell (201) and which are adapted to feed a respective output current to a first (204) or a second output contact (206) in dependence on a logic state of the intermediate storage cell, wherein a first of two outputs of an intermediate storage cell (202) is connected by way of an input resistor (220) to a first signal terminal (208.1) of a first transistor (208) and a second of the two outputs of the intermediate storage cell (202) is connected by way of an input resistor (218) to a first signal terminal (210.1) of a second transistor (210), the respective first signal terminals of the first and second transistors are additionally connected by way of a constant current source (212 and 214) to a ground terminal (216), and wherein a respective time-constant bias voltage is applied at a respective control terminal (208.2 and 210.2) of the first and second transistors.