Parallel DAC Filter Circuit for GHz Timing Margin
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Solution Overview
Problem
Conventional transmission filters face difficulties in securing a timing margin for high-speed communication systems, particularly when operating at several GHz, due to delays caused by resistance and parasitic capacitance components, making it challenging to maintain proper timing between the clock and data signals.
Innovation Solution
A filter circuit configuration that includes multiple digital filters and DACs performing parallel processing, with a PLL circuit supplying a reference clock and a frequency divider generating a frequency-divided clock for the DACs, allowing for shared clock buffers and a comparator to adjust delays, ensuring a stable timing relationship between data and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional transmission filter is used for high-speed communication systems of several GHz, then the communication speed is improved, but the timing margin becomes insufficient due to delays in clock lines
Solution Approach 1:
The patent divides the clock distribution system into multiple segments: a master clock buffer that generates the reference clock, and multiple slave clock buffers that are distributed to different DACs. Each slave clock buffer receives the clock from the master and distributes it locally, reducing the impact of resistance and parasitic capacitance in long clock lines.
Solution Approach 2:
The patent introduces slave clock buffers as intermediary elements between the master clock buffer and the DACs. These slave clock buffers act as local clock sources that are synchronized to the master clock, thereby mediating the timing relationship and reducing the direct impact of long clock line delays on the DAC operation.
2Ease of operation
If individual clock lines are supplied to each digital filter and DAC from the PLL circuit, then each component receives its clock, but delays due to resistance, parasitic capacitance, and buffers make timing design extremely difficult
Solution Approach 1:
The patent merges the clock distribution function into a hierarchical structure where a single master clock buffer serves multiple slave clock buffers, which in turn serve multiple DACs. This consolidation reduces the number of independent clock lines from the PLL circuit and simplifies timing design by creating a synchronized clock domain.
Solution Approach 2:
The master clock buffer serves a universal function by providing the reference clock to multiple slave clock buffers, which then distribute clocks to various DACs. This multi-functional clock distribution system reduces complexity while maintaining proper timing relationships across all components.
3Productivity
If the clock is supplied to digital filters and DACs individually from the PLL circuit, then each component operates independently, but timing restrictions become extremely strict at several GHz speeds
Solution Approach 1:
The patent implements preliminary synchronization by having slave clock buffers receive and synchronize to the master clock buffer before distributing clocks to DACs. This preliminary action establishes a known timing relationship in advance, allowing high-speed operation with adequate timing margins.
Data Source
AI summary
A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.