Parallel DAC Architecture for High-Resolution High-Speed Output
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) face a trade-off between high-resolution and high-speed performance, often resulting in slower speeds, higher costs, and excessive noise, making them impractical for use in source measure units (SMUs).
Innovation Solution
A high-resolution, high-speed DAC design featuring multiple parallel gain stages combined through a single integrator stage, allowing for high update rates and low latency, with decade-weighted thresholds and resistors to achieve nearly 18-bit performance at 150 MHz or greater, and incorporating filters to reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DACs use high-resolution design, then resolution is improved, but speed and update rate deteriorate
Solution Approach 1:
The DAC is divided into multiple parallel gain stages (first through Nth gain stages), each handling a portion of the digital signal. This segmentation allows simultaneous processing of multiple signal components, achieving high resolution through parallel computation while maintaining high update rates, as each stage operates independently at high speed.
2Speed
If conventional DACs use high-speed design, then update rate is improved, but resolution deteriorates
Solution Approach 1:
Multiple parallel gain stages are merged through a summing node that combines their outputs. This merging allows the system to achieve high resolution by summing multiple high-speed signal paths, effectively combining the advantages of parallel high-speed processing with accurate signal reconstruction, achieving nearly 18-bit performance at 150 MHz.
3Measurement precision
If conventional DACs increase resolution, then precision is improved, but manufacturing cost deteriorates
Solution Approach 1:
The patent uses multiple copies of the same gain stage circuitry (first through Nth gain stages) operating in parallel. Instead of using a single complex high-resolution converter, the system creates multiple simpler, identical stages that can be manufactured using standard processes, then combines their outputs to achieve high resolution, significantly reducing manufacturing costs.
4Speed
If conventional DACs use parallel processing to increase speed, then update rate is improved, but device complexity deteriorates
Solution Approach 1:
Each gain stage uses decade-weighted thresholds and resistors with specific local characteristics optimized for its position in the parallel structure. This local optimization allows each stage to contribute efficiently to the overall high-speed performance while maintaining manageable complexity through standardized design patterns that can be replicated across stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-resolution, low-noise analog output at high sample rates, reducing manufacturing costs and improving performance in SMUs by balancing comparator numbers and signal latency, achieving performance equivalent to a nearly 18-bit, 15 Msps DAC.
Implementation Method 1
An integrator stage receives an output from each of the gain stages. The integrator stage sums and filters the multiple outputs of the gain stages into a single analog output signal.
Implementation Method 2
Each comparator compares the digital value to a unique threshold. That is, the threshold received at each comparator is different.
Data Source
AI summary
A digital-to-analog converter, including an input to receive a digital signal; a first comparator configured to receive the digital signal and output a first signal based on the digital signal and a first threshold; a second comparator configured to receive the digital signal and output a second signal based on the digital signal and a second threshold, the second threshold different from the first threshold; and an integrator configured to receive the first signal and the second signal and integrate the first signal and the second signal into an analog signal that represents the digital signal.