Parallel Multi-DAC Frequency Shifting Beyond Fs/2

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Solution Overview

Problem

Conventional multi-DAC systems with multi-phase clocking and uniform phase offsets suffer from a lowpass filter characteristic that limits the output signal to between 0 and Fs/2, leading to significant gain variations when compensating for desired and undesired images, especially when repeaters are used for up-sampling.

Innovation Solution

A low complexity high-speed multi-DAC system is designed with a plurality of DACs arranged in parallel, each having a different analog phase response, and a circuit that multiplies the digital signal by a series of +1 and -1 values to shift the peak frequency response away from DC to a non-DC frequency, eliminating the lowpass filter characteristic without gain compensation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If multi-phase clocking with uniform phase offsets is used in parallel DAC architecture, then direct connection of DAC outputs is permitted and image suppression is enabled, but the frequency response exhibits lowpass filter characteristic that limits output signal to between 0 and Fs/2

Engineering Contradiction:
Improvedirect connection of DAC outputsVSAvoidoutput frequency range
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent applies different phase offsets to different DAC paths instead of using uniform phase offsets. Specifically, first and second phase offsets are applied to first and second DACs respectively, where these offsets are different from each other. This local differentiation in phase offset quality allows each DAC path to have customized phase characteristics, enabling the system to generate output signals beyond the traditional Fs/2 limit while maintaining direct connection capability.

Inventive Principle:
Principle #3Local quality

2Device complexity

If conventional multi-DAC system is used with uniform phase offsets, then system complexity is reduced, but significant gain variations occur when compensating for desired and undesired images

Engineering Contradiction:
Improvephase offset configurationVSAvoidgain variation compensation
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent changes the phase offset parameters from uniform values to different values for different DAC paths. By setting specific different phase offsets (first phase offset for first DAC, second phase offset for second DAC), the system achieves better control over image suppression and gain variation compensation. This parameter differentiation allows the system to maintain lower complexity while reducing gain variations, as the different phase offsets naturally provide better separation of desired and undesired images.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If repeater is used for up-sampling in conventional multi-DAC system, then data rate is increased, but the lowpass filter characteristic is applied twice causing exacerbated gain variation

Engineering Contradiction:
Improvedata rateVSAvoidgain variation
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies different phase offsets at different stages of the signal processing chain to counteract the cumulative lowpass filter effect. By using non-uniform phase offset configuration in the repeater stage (different from the first stage), the system compensates for the repeated lowpass filtering. This local adaptation of phase offset quality at each processing stage allows high data rate operation while preventing the exacerbation of gain variations that would otherwise occur with repeated lowpass filtering.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8618969B2Low complexity high-speed multi-DAC system
Publication Date: 2013.12.31 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US8618969B2 patent drawing
  • US8618969B2 patent drawing
  • US8618969B2 patent drawing

AI summary

A multi-DAC system includes a plurality of DACs arranged in parallel for converting a digital signal to an analog signal, each DAC path having a different analog phase response. The system further includes a circuit for multiplying the digital signal input to at least some of the DACs by a multiplicand sufficient to shift a peak of a frequency response of the multi-DAC system to a non-DC frequency. For example, a series of +1 and/or −1 digital values can be used to multiply the digital signal so that the signal has the same number of bits pre and post multiplication. The multiplicand can include a constant series of +1 or −1 digital values, or a time-varying series of +1 and −1 digital values. In each case, the peak frequency response of the multi-DAC system can be shifted away from DC to a multiple of the sampling frequency of the DACs.