Parallel Capacitive-Resistive DAC Circuit for Wider Passband
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital-to-analog converters face bandwidth limitations, particularly when a capacitive voltage division DAC needs to drive a resistive load, resulting in suppressed frequency ranges.
Innovation Solution
A digital-to-analog conversion circuit comprising a capacitive voltage division type DAC and a resistive load type DAC connected in parallel, forming a common RC load, which extends the frequency passband by combining their characteristics, allowing a continuous passband with both DACs operating on the same digital input sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a capacitive voltage division DAC is used to achieve wide bandwidth, then frequency response is improved, but when driving a resistive load the output is suppressed at low frequencies
Solution Approach 1:
The patent combines a capacitive voltage division DAC and a resistive voltage division DAC in parallel configuration. The capacitive DAC provides high-frequency response while the resistive DAC provides low-frequency response, and their outputs are summed to produce a composite signal with extended bandwidth and improved output quality across the entire frequency range.
2Device complexity
If a single DAC type is used to simplify the circuit, then device complexity is reduced, but bandwidth is limited
Solution Approach 1:
The patent segments the bandwidth coverage by using two different DAC types with complementary frequency characteristics. The capacitive DAC handles the high-frequency portion of the spectrum while the resistive DAC handles the low-frequency portion, allowing each DAC to be optimized for its specific frequency range rather than requiring a single DAC to cover the entire bandwidth.
Data Source
AI summary
A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.